I.� Introduction and summary of research

A. purpose

The specific purpose of this research was to evaluate the performance, correctness, and ease of use of the SRC-6E reconfigurable computing system built by SRC Computers, Inc., for implementing false radar images.� The more general purpose was to aid in establishing a broad base of knowledge on what types of applications are appropriate for implementation on this type of machine.� The task of generating false radar images provides a readily available yet suitably complex algorithm for implementation on the SRC-6E.� The research builds on previous work [1].� The algorithm chosen was based on a custom chip design previously developed by a faculty/student research team at the Naval Postgraduate School which creates false target radar images.� A C language program, written by Professor Douglas Fouts, was also available to use as a standard for comparing the accuracy of results throughout the research.

B. summary of research

Reconfigurable computing is defined as "the capability of reprogramming hardware to execute logic that is designed and optimized for a specific user�s algorithms" [2]. The SRC-6E reconfigurable computer is a Linux-based system consisting of two sides labeled A and B which each contain motherboards holding dual Intel P3 Xeon 1-GHz processors, 1.5 gigabytes of memory, and a SNAP interface card.� The SNAP card is a custom interface card which plugs into a motherboard DIMM memory slot and provides connections to the MAP board which is located in a third section of the system.� A single MAP board consists of two independent MAPs.� MAP, a registered trademark of SRC Computers, Inc., is the name for the custom hardware.� Each MAP consists of three Xilinx Virtex-II-series XC2V6000 FPGAs and 24 megabytes of memory.� One of the FPGAs [NCR1] is reserved for control logic while the other two, available for user programs, are called "user logic".� The memory is split into six equal banks, labeled A through F, of 4 megabytes each.� The user FPGAs are connected to a fixed 100-MHz clock.

�� Code written in the hardware description languages Verilog and/or VHDL can be ported to the SRC-6E with only minor changes.� Several support files are required to help the code exploit the user logic.� These files primarily describe the interfaces to the code.� The algorithm selected for the research described here was written in VHDL and converted for use on the SRC-6E.

To evaluate the effectiveness of the SRC-6E, timing data was collected from several implementations of the false radar target algorithm.� The first implementation was the executable created on the SRC-6E which uses the reconfigurable user logic.� The second implementation was a C program which performed the same functionality as the VHDL code.� This code was compiled and executed on a 3-GHz Pentium 4 system, using 2 gigabytes of DIMM memory and the Windows XP Professional operating system.� The machine used was the same one as the previous implementation to allow comparison of results.� The third implementation was the same C program running on the 1-GHz Xeon processor on a Linux based SRC-6E, but not using the MAP.� Several input data sets were used in testing.� Each data value consisted of a 5-bit number, written as two hexadecimal digits, which represented an intercepted radar signal.� Data sets containing 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16284, 32786, 65536, 131072, 262144, and 500000 data values were used.� Five timing runs were conducted for each data set on all three data sources.

The timing data shows the SRC-6E MAP execution time is extremely fast, even for very large data set sizes.� However, the total execution time for the SRC-6E VHDL macro takes considerably longer.� The extra time represents delays in the system to prepare and transfer the data in and out of the MAP which cause the SRC-6E execution time to be longer for most input set sizes, initially by an order of magnitude. Comparison of the MAP execution times for the previous 4-bin macro with the new 4-bin macro shows an improvement for large input set sizes, verifying that the new interface design is more efficient.

As input set size is increased the timing results begin to converge.� The overhead in the SRC VHDL macro clearly dominates the results for smaller sample set sizes.� However, for larger sample set sizes, the overhead time is amortized over the total time to be nearly insignificant.� The 64-bin model shows the SRC macro total execution time catching up to other benchmark platforms and would likely beat them if the sample set size could be further increased.� However, this is not possible with the current macro design due to the memory design of the SRC-6E hardware.� The 128-bin model shows the SRC macro total execution time beating all benchmark platforms after approximately 50,000 sample set size.

Programming the SRC-6E to use user-defined macros requires knowledge of high-level programming languages, hardware description languages, hardware component design, and synthesizability.� Relatively few people possess all of these skills to use the system effectively without first receiving significant training.� However, programming the system using only high-level languages of C or Fortran is possible which widens the potential user base to many more people.� More research needs to be performed to determine if either method produces more effective solutions.

The SRC-6E has a relatively steep learning curve.� There are a few examples in the documentation and a very small body of work in place using the system.� The errors generated by the system during development are not intuitive and cannot be solved without previous experience with solving the same errors.� There are no development tools in place to assist novice users in programming the system.� More research is required to see how much experience on the system is required to prevent and or recognize these types of errors quickly.

The development time to implement solutions on this system appears to be high, primarily due to the steep learning curve and lack of development tools.� More research must be performed to quantify the development time and see how it improves once a group of experienced repeat users is grown.� No research has yet been performed with large projects, employing multiple programmers, to see if the total project time can be reduced effectively.

Since it is pipelined and supports parallel processing, the chosen implementation of the false-target radar-imaging algorithm appears to be one that would benefit from a reconfigurable computer.� The current implementation has shown the hardware�s effectiveness for a highly parallel process with large input data sets.� However, the steep learning curve and high development time are unlikely to change until more user-friendly development tools are created for the system.

C. Remaining chapter outline

The following outlines the remaining chapters which roughly follow the major steps that were taken throughout the research:

� Chapter II provides background information and review of previous research.

� Chapter III discusses the SRC-6E architecture, programming environment, and documentation.

� Chapter IV discusses modifications to the original VHDL macro programmed using VHDL.

� Chapter V discusses porting the VHDL code to SRC-6E environment.

� Chapter VI presents the data collection methods and analysis.

� Chapter VII provides conclusions and future work recommendations.

� Appendix A contains the modified C program originally written by Professor Douglas Fouts which was used a standard for output correctness and as a source of timing data.

� Appendix B contains the VHDL code for all range bin models.

� Appendix C contains the support files required to implement the VHDL code on the SRC-6E.

� Appendix D contains all of the timing data collected during the research.

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II. background and previous work

A.�� introduction

This chapter discusses background information and reviews previous work, including the basics of the false radar imaging algorithm, the benefits and costs of pipelining the algorithm, use of the chip design and C program in both the current and previous research and gives an overview of the major steps taken to improve, expand and test the algorithm using the SRC-6E.� The algorithm used in the previous research was based on a custom chip design previously developed by a faculty/student research team at the Naval Postgraduate School which creates false target radar images.� The same C language program, originally written by Professor Douglas Fouts, was again used as a standard for comparing the accuracy of results throughout the research.

B.�� False target Radar imaging algorithm

The algorithm works by splitting a false target image into several range bins, as shown in Figure 1, where a ship is split into four range bins.

Figure 1.� False Target Radar Imaging Algorithm Usage

Each range bin represents a portion of the vessel based on the distance from the radar source.� Greater resolution can be achieved by having a greater number of range bins for a given false target.� It can be observed from the geometry that the radar-signal travel distance is different for each range bin.�

Based on knowledge of a ship�s radar image, an operator can set phase rotation and gain constants for each range bin. The algorithm begins with the interception and sampling of an interrogating radar pulse.� The sample phase is then rotated by adding a rotation constant to it.� Next, the sine and cosine are calculated.� The gain is then applied to the results by multiplying by a gain value.� The results of each range bin are then summed up to produce a radar reflection signal at a given time.� With proper use, the ship can be made to appear in a false position, be of a different type of target, or to appear to be traveling with other ships.

C.�� False-target radar-imaging chip design

The false-target radar-imaging chip consists of a 6-stage pipeline which performs all necessary functions to create a false radar reflection for a single range bin.� Figure 2 shows the signal flow through the slightly simplified version as was implemented during the previous research.

Figure 2.� False Target Radar Image Chip Signal Flow

The basic steps of the algorithm are performed as follows:

1. The phase sample enters into register 3.

2. The phase rotation value enters into register 1, is then loaded into register 2, and is then added to the phase sample at adder 1.� The results are then loaded into register 4.

3.�� The contents of register 4 enter the lookup table (LUT) and Sine and Cosine results are calculated.� The remainder of the pipeline is split into two identical portions for each data result.� The following steps outline the path for the Sine result.

4.�� The gain value enters at register 5, is then loaded to register 6, and proceeds to shifter 1 where it controls how the contents of register 7 are shifted before they proceed to register 9.� This accomplishes modulo-2 multiplication.

5.�� The result from a preceding range bin enters at register 11 and is added to the contents of register 9 in adder 2 before proceeding to register 13.

6.�� The contents of register 13 are now available as output Q if this is the last range bin in the series or are sent to register 11 of a following range bin.

The control logic block receives signals URB (use range bin), PSVin (phase sample valid input), and ODVin (output data valid input).� These signals are used to create the CLR13 (clear 13-bit register), CLR17 (clear 17-bit register), PSVout (phase sample valid output), and ODVout (output data valid output).

The internal design of the control logic is shown in Figure 3.� The CLR13 and CLR17 signals are used to clear the register contents at the appropriate time in the pipelines when they do not contain valid data.� This occurs during pipeline startup and shutdown.� The PSVout signal is present to show the DRFM signal is valid.� The ODVout signal is present to show that outputs Q and I contain valid data.� The URB signal is present to allow the operator to disable a range bin.� Figure 4 shows the signal flow when four range bins are connected together.

Figure 3.� Internal Design of the Control Logic

D.�� false-target radar-imaging program design

The false-target radar-imaging program was written in the C language.� It performs the same arithmetic calculations as the false radar imaging chip but uses nested loop iterative structures instead of pipelines.� While the chip requires a separate pipeline for each range bin, the program simply adds additional length to the appropriate arrays, trading off memory utilization for computational logic.� Table 1 shows how the results of each of four range bins with an input of N samples are placed into the two dimensional array created by the program.� Each row of the table is then summed up to produce the false target radar signal results.

Figure 4.� Signal Flow for Four Cascaded Range Bins

Bin 0	Bin 1	Bin 2	Bin 3
Sample 1 Results	0	0	0
Sample 2 Results	Sample 1 Results	0	0
Sample 3 Results	Sample 2 Results	Sample 1 Results	0
Sample 4 Results	Sample 3 Results	Sample 2 Results	Sample 1 Results
�	�	�	�
Sample N Results	Sample N-1 Results	Sample N-2 Results	Sample N-3 Results
0	Sample N Results	Sample N-1 Results	Sample N-2 Results
0	0	Sample N Results	Sample N-1 Results
0	0	0	Sample N Results

Table 1.� False-Target Radar-Imaging Program Example Using Four Range Bins

The program was used as both a trusted source for results to test the research against as well as used in the timing comparisons discussed in Chapter VI.� The full code for the program can be viewed in Appendix A.

E.�� benefit and cost of pipelining algorithms

The implementation of the false-radar imaging-algorithm has each range bin�s function split over 5 pipeline stages.� The output of each range bin is then chained into the next in the final pipeline stage.� This section will discuss the benefits and costs of pipelining.

1.�� Background

Pipelining allows work that involves repetition to be performed in parallel, reducing the total completion time.� It is most effective when the work can be separated into tasks of equal length.� However, in reality, work seldom splits into subtasks of equal length.� Since the completion time for each stage varies with the task it performs, some delay is required at the end of each stage, so that slower stages have time to complete their task before receiving new work.� Each of these tasks then becomes a pipeline stage where a portion of the total job is performed for each item passing through the pipeline.� Each stage receives a result from the previous stage, performs its task, and then passes the new result to the next stage.

For work that involves arithmetic functions performed by a computer, each pipeline stage consists of the logic to perform the subtask and a register which stores the result until the next stage is ready for it.� A clock performs coordination of the entire pipeline by allowing the registers to all fill at the same time.� The clock can only run as fast as the slowest pipeline stage.� The speed of each stage includes the time to complete the function as well as the delay time caused by the register itself.

2.�� Pipeline Benefits

Pipelines have two major benefits.� First, as previously discussed, they allow multiple repetitive tasks to be performed in parallel which reduces the total completion time.� Second, pipelines can allow computer logic to run at a higher clock speed.� More complex logic functions require more time to complete.� When the total time required is longer than the desired clock speed, the function can be broken into smaller pieces and placed in a pipeline.

3.�� Pipeline Costs

Since functions can rarely be broken into equal subtasks and pipeline registers introduce some delay, the total time to complete a function in a pipeline will always be longer than the time to do it once without a pipeline.� However, when the function must be repeated the pipeline can become efficient.� The point where the pipeline becomes efficient can begin no sooner than when the number of repetitions exceeds the number of stages.� Also, if the function is not split up into fairly equal subtasks and/or the register delay is high, the onset of pipeline efficiency can be delayed even further.� Pipeline speedup of a k-stage pipelined function over an equivalent non-pipelined function is defined as [3]:

, where n is the number of repetitions.

The implementation of the false-radar imaging-algorithm has each range bin�s function split over five pipeline stages.� The output of each range bin is then chained into the next in the final pipeline stage.� This creates a complete pipeline length of N+4, where N is the number of range bins implemented.�� Figure 5 shows the pipeline speedup for the number of range bins implemented in this research, using N for k and number of samples for n.

Figure 5.� Speedup vs. Number of Range Bins.

The plots shows speedup increases as the number of samples is increased.� For n>>k, maximum speedup of k is achieved, meaning k tasks are efficiently performed at the same time.� For low n, the pipeline length is too long to be efficient.� This phenomenon can be viewed in the data presented in Chapter VI.

F.�� summary of new research

Previous work implemented and tested four range bins.� For simplicity, the previous design passed all the range bin programming data with each new radar sample.� However, this was inefficient since the programming data does not change over a given set of radar samples.� For each 5-bit sample, 40 bits of repetitive programming data was reentered, (10 per range bin).� The interface to the MAP consists of 6 banks of 64-bits, of which at least one must be designated for output, leaving at most 320 bits for input.� With the expansion to 16 range bins, half of the input bandwidth would have been consumed by unnecessary, repetitive programming data and further expansion beyond 16 bins would be impossible within the provided bandwidth.� The current research implements 4-, 8-, 16-, 64- and 128-range bin versions using a new design which allows the programming data to be sent to the macro only once for each set of radar samples.

This chapter discussed background information and previous work.� The next chapter will discuss the hardware, software, and documentation, of the SRC-6E reconfigurable computing system.��

III. SRC-6E architecture and software environment

A.�� Introduction

This chapter provides a brief overview of the hardware, software, and documentation, of the SRC-6E reconfigurable computing system.� Reconfigurable computing is defined as �the capability of reprogramming hardware to execute logic that is designed and optimized for a specific user�s algorithms� [2].

b.�� SRC-6E hardware overview

The SRC-6E computer consists of two independent Linux computers (labeled A and B) and a MAP board, (see Figure 6).

Figure 6.� SRC-6E System Diagram (After Ref. 4.)

MAP, a registered trademark of SRC Computers, Inc., is the name of the custom reconfigurable hardware.� Each independent Linux computer contains a motherboard holding dual Intel P3 Xeon 1-GHz processors, 1.5 gigabytes of memory, and a SNAP interface card.� The SNAP card is a custom interface card which plugs into a motherboard DIMM memory slot and provides connections to the MAP board which is located in the MAP Chassis.� A single MAP board consists of two independent MAPs.� A block diagram of a single MAP is shown in Figure 7.� A MAP consists of three Xilinx Virtex-II-series XC2V6000 FPGAs and 24 megabytes of memory (labeled OBM on Figure 7).

Figure 7.� MAP Interface Block Diagram (From Ref. 4.)

One of the FPGAs is reserved for �control logic� while the other two, available for user programs, are called �user logic�.� The OBM memory is split into six equal banks, labeled A through F, of 4 megabytes each.� The user FPGAs are connected to a fixed 100-MHz clock, which seems overly restrictive.� According to Xilinx product specification sheets, the Virtex-II-series FPGAs can ran at clock speeds as low as 1 MHz and upwards of 400 MHz [5].� Programmer control of the clock speed on the SRC-6E would make the system more flexible.� Each MAP also has a chain port which can be used for direct I/O to the user logic, but was not used during this research.

c.�� software environment

1.�� Operating System

The operating system for the SRC-6E is Red Hat Linux, which has been augmented with custom drivers and libraries to support the MAP and SNAP hardware.� The built-in graphical text editor in Linux is called GEdit.� Programmers experienced with UNIX can use the standard line type text editors such as VI if they choose.� Both contain the minimal functionality required of a text editor to write the required files for the SRC-6E.�

2.�� Programming Environment

The programming environment for the SRC-6E is called Carte.� Carte allows a user to write code in a high level language, either C or Fortran, that directly targets the user programmable FPGAs in the MAP.� In addition, users can write their own �macros� using the hardware definition languages Verilog and/or VHDL.� At compile time, all user code and macros are linked together into a single executable file. Carte includes standard compilers for the Intel microprocessors as well as custom MAP compilers for both Fortran and C.� Synplify Pro software by Synplicity, Inc. is used for FPGA place and routing.� This program normally runs under Windows version but is executed in the Linux environment using a Windows emulator called Wine.

Since Carte relies on the built-in Linux editors, the SRC-6E programming environment does not have any of the modern features a programmer expects from editors available in products such as Microsoft�s Visual C++ or Borland�s J-Builder.� Lack of syntax and error checking in the programming environment is a serious drawback when using this system.� Some error messages are produced at compile time, but they are cryptic at best, especially for someone not used to the Linux environment.� There are several file types which must interact during the compile process, as will be discussed in Chapter V.� The intricate details of these files can be quite confusing and it is often difficult to identify which file contains the problem based on the error messages given at compile time.� Rudimentary checking of these files within a custom editor would greatly improve the entire programming process.

d.�� major documentation

The documents discussed here come with the SRC-6E to aid in its programming.

1.�� SRC-6E C Programming Environment Guide

Driver code must be developed to create the interface to the user logic.� This document describes how to write this code using the C language [6].

2.�� SRC-6E Fortran Programming Environment Guide

Similar to the C Programming Environment Guide, this document describes how to write similar code using the Fortran language [7].

3.�� SRC-6E MAP Hardware Guide

This document contains hardware implementation specifics of the MAP which are well below the level required for users to successfully program the SRC-6E [4].

4.�� SRC-6E MAP Macro Developers Guide

This document discusses general information on the use of the Macro Data Sheet Library, including naming conventions, interfaces, fanout and combinatorial delays [8].

5.�� Macro Data Sheet Library

The library contains data sheets for all macros developed by SRC for the SRC-6E.� A list of all currently supported macros is available in a technical note, Ref. 9.� The macros can be used like regular function calls in the chosen programming environment language (C or Fortran).� The macros include all basic math and logic functions currently supported by the environment.� There are also several support macros which include, among others, various macros for combining and splitting data structures.

This chapter provided an overview of the hardware, software and documentation of the SRC-6E computer.� The next chapter will discuss development and testing of the VHDL code used in the research.

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iV. Development and testing in vhdl with aldec active-hdl 5.2

A.�� introduction

This chapter describes the development of the false-target radar-imaging macros in VHDL before they were ported to the SRC-6E environment.� The final code used to implement 4 range bins in the previous research was used as a starting point and is hereafter referred to as the �old macro�.� Development of the macros was performed in a Windows XP environment using Aldec Active-HDL 5.2 software.

B.�� modifications to previous macro

The old macro used two 64-bit inputs and a single 64-bit output.� Assuming that a reduction in overhead would improve their efficiency, the new macros were developed to use only a single 64-bit input and output.� Other modifications included addition of the PRB and UNP signals and internal connections of the URB signal within the range bins.� 4-, 8-, 16-, 64- and 128-range bin versions were created.� The code for this section can be viewed in Appendix B.

1.�� Overhead Reduction

�� To reduce the input bandwidth, it was necessary to send in the programming data only once for each set of radar samples.� This was accomplished by complete redesign of the interface with implementation of the PRB and UNP signals.� These signals were present in the original chip design but were not implemented in the old macro.

2.�� PRB Signal

The PRB signal, which stands for �Program Range Bin,� was originally intended to signal a specific range bin to accept new programming.� As implemented in this interface, it signals the start of a programming sequence where four range bins are programmed per clock cycle until all are programmed.� Thus for the sixteen bin model it takes 4 clock cycles to program all range bins.� The PRB is delayed through a shift register which is appropriately sized for the number of range bins.� Each group of four range bins beyond the first requires a bit.� A three bit shift register is used for the 16 range bin macro, one bit for the 8 range bin macro, and no shift register is necessary for the 4 range bin macro.� All range bins are sent programming data at the same time, but the delayed PRB signal causes only the appropriate group of range bins to load the data.

3.�� UNP Signal

�� The UNP signal, which stands for �Use New Programming,� was originally intended to signal each range bin one at a time to begin using its new programming.� The UNP signal was not implemented in the old macro.� As implemented in the new macros, it signals all range bins to simultaneously use their new programming.� The UNP signal is normally low.� Taking the UNP signal high for one clock signals the macro to use the new programming data previously loaded by a PRB programming sequence.

4.�� URB Signal

The old macro used a URB signal which stands for �Use Range Bin.�� Intended as a single bit for each range bin to signal the control logic as to whether or not to use a particular range bin, this signal is programmed during the PRB programming sequence.� When low, the output of a range bin is not included in the overall output.� The old macro assumed that all four range bins would be used and had this signal tied high.� The new macro designs have the URB signal internally connected to allow its full intended use.

5.�� Four Range Bins

The code for four range bins was created by instancing the original single range bin code and creating a new, more efficient interface.� The signal flow of four range bins is shown in Figure 4.� The code was verified by comparing the output to the C program run on the same data set.� This model was created to draw a timing comparison between the old macro and the new design.� This will determine if the reduction in the interface has any affect on the overall timing.

6.�� Eight Range Bins

A system with eight range bins was created by instancing eight of the single range bins previously tested.� The code was verified by comparing the output to the C program run on the same data set.� This model was developed as an intermediate size for collection of timing data.

7.�� Sixteen Range Bins

A system with sixteen range bins was created by instancing sixteen of the single range bins with an appropriate interface.� The code was verified by comparing the output to the C program run on the same data set.� This model was the original goal of the new research.� Through reduction of the interface overhead by 1/3 and increase of the number of pipelines by a factor of 4, it was hoped that the SRC-6E would show an improvement in timing as compared to the other benchmarks.

7.�� 64 Range Bins

A system with 64 range bins was created by instancing 64 of the single range bins with an appropriate interface.� The code was verfied by comparing the output to the C program run on the same data set.� This model was developed because of the unexpectedly low chip usage by the previous models which will be discussed in the next chapter.

8.�� 128 Range Bins

A system with 128 range bins was created by instancing 128 of the single range bins with an appropriate interface.� The code was verified by comparing the output to the C program run on the same data set.� This model was developed after the 256 range bin model would not fit in the user logic area.

9.�� 256 Range Bins

A system with 256 range bins was created by instancing 256 of the single range bins with an appropriate interface.� The code was verified by comparing the output to the C program run on the same data set.� This model was developed in an attempt to determine an upper bound for how many range bins would fit within the user logic area.

This chapter discussed VHDL code development.� The next chapter will discuss porting the code to the SRC-6E.

V.� Porting the vhdl code to the src-6e

A.�� introduction

This chapter discusses the porting of the VHDL code to the SRC-6E and the required support files.� Also discussed are changes that were required to the original code to make it compatible with the SRC-6E.

B.�� the src-6e file types

The process of writing code to target the user logic requires several file types.� To import a user macro from either VHDL or Verilog, five files must be created: .info, .box, .mc, .c, and the makefile.� Using only the last three, one can write code that targets the user logic without using a user defined macro.� Examples of these file types can be viewed in Appendix C, which contains the final versions of all the files used.

1.�� .info

This file type is required whenever a user macro is used.� It contains the following information:

� Macro name

� Macro type � stateful, external, and pipelined

� Latency � a number stating how many clock cycles before valid output is generated by the macro.

� List of inputs and outputs

The file type �.info� is a naming convention and is not required.� Any filename can be used as long as it matches that listed in the makefile.

2.�� .box

This is another file type that is required only when using a user-defined macro.� It is a Verilog style description of the input and output variables of the macro.� The Verilog description is necessary for both VHDL and Verilog macros.� As with the .info type, the .box name is only by convention.

3.�� .mc

This file type is C code written to target the user logic.� All code in this file will be implemented in hardware along with the user macro.� Using this file type, it is possible to write code for the hardware using only the high-level language C without using any user-defined macros defined with a hardware description language.

4.�� .c

This file type is regular C code which provides the interface between the operating system and the hardware code defined in the .mc file.� Code implemented in this file is executed on the Xeon processors.

5.�� makefile

This file is used by the command �make� when all the files are compiled and linked.� It contains all of the file names and paths used, as well as the desired final executable name.� Compiler flags and options can also be stated in this file.

6.�� .vhd

This file type is for VHDL macro files.� In general, it is safest to merge multiple files into one.� However, it is possible to build with separate files as long as they are listed in the proper order in the makefile.� The compiler appears to be single pass so the files must be in the order they are used, with the lowest order file listed first.

7.�� Other Types

Two other file types can be used by users programming the user logic:� .f, which is a Fortran file, and .v, which is a Verilog file.� These file types were not used during this research.

C.�� code development

Porting of the macro code began with creation of the required support files previously mentioned.� Modifying the support files from the old macro was fairly simple.� Only the .c interface file required significant rewrite to match up with the new macro interface.� The code went through three major versions and several revisions.

1.� Version 1.0

The sixteen-range-bin VHDL code was imported to the SRC-6E.� The required support files were generated by modifying the old macro files to support the new design, this proved trivial compared to the long trial and error process reported in the previous research.� However, during the make process, the SRC-6E reported a final clock speed of 78.5 MHz, well below the required minimum of 100 MHz.� Without surprise due to the timing failure the generated executable did produce the proper output.� This version implemented the programming sequence using a finite state machine with four states using only the UNP signal to reset the state to zero.� While this version created the proper output with the Aldec software, it generated too much delay when implemented in hardware on the SRC-6E.

2.� Version 1.1

�� An eight-range-bin version was created to reduce the macro complexity for troubleshooting.� After verification in Aldec of the proper output it was compiled on the SRC-6E.� This version reported a final clock speed of 84.6 MHz and also generated incorrect output.

3.� Version 1.2

A four-range-bin version was created to further reduce the macro complexity for troubleshooting.� After verification in Aldec of the proper output it was compiled on the SRC-6E.� This version reported a final clock speed of 85.1 MHz and also generated faulty output.� Since the old macro had generated proper four-range-bins output on the SRC-6E it was determined that the finite state machine method would not work on the SRC-6E, presumably due to the style of programming it and not failure of the SRC-6E.� After discussion with SRC technical support, the need for a simpler more direct way of implementing the interface became apparent.

4.� Version 2.0

Review of the actual functionality required by the state machine showed that the same tasks could be performed with simpler components.� Since the states were only transitioned in numerical order, one per clock, the same function could be performed with a counter.� Since the new version would require a significant redesign a review of the original chip design was conducted to see if the macro implementation could be brought closer to the original design.� During the review it was discovered that if the original PRB and UNP signals were implemented properly, a simple shift register could perform all of the necessary functions to direct the programming input as required.� The new design was implemented and verified in Aldec to produce the proper output.� After porting the new macro to the SRC-6E and modifying the .c file to support the new interface, the SRC-6E produced the proper sixteen-range-bin output for the first time.� Following the same basic design, new 8- and 4-range bin macros were rapidly created and verified.

5.� Version 3.0

After unexpectedly low FPGA usage for the 8- and 16-bin macros, only 12% and 16%, a 64-bin macro was implemented.� The new version demonstrated an FPGA usage of 38%.� A 256-bin version was then attempted but it would not fit within the user logic.� Finally, a 128-bin version was created which demonstrated a usage of 68%.

d.�� synthesizablity

As noted in the original research, synthesizability was a problem during the design process.� Synthesizability is a style of hardware description language programming which allows the available layout tools to properly convert the code for hardware implementation on an FPGA.� During the design of the code, the Aldec software was only used to simulate the VHDL code.� Therefore, it only tested the code for functionality and did not consider if the code could actually be implemented in hardware.� Problems with the state machine design resulted in synthesizability problems which were resolved with a redesign of the interface.� The root cause of this was inexperience with both the VHDL language and the concept of synthesizability.

E.�� FPGA Utilization

As previously noted, FPGA utilization was much lower than expected.� Based on the 4-bin�s 10% usage, slightly over 20% and 40% were expected for the 8 and 16 bin models, based on linear scaling of the number of additional pipelines implemented by the two larger models.� The 12% and 16% usages show that the Xilinx software is performing some unexpected and very effective optimization of the VHDL code which causes the actual usage to be much lower than the original estimations.� The 64- and 128-bin versions showed usage of 38% and 68%.� A 256-bin version was attempted but after 3 days of compiling failed with a usage of 99% with a little over 500 signals left to route.� Thus 256-bins almost fit within the user logic area.� However, it should be noted that this version had multiple timing failures resulting in a clock speed of only 32.8 MHz which would not have produced correct results.� Figure 8 is a plot of actual FGPA usage vs. the number of bins.� Two best fit plots, one exponential and one second order polynomial are added to predict the FPGA usage for macros with other numbers of bins.� The polynomial curve seems to most closely match the actual data.�

Figure 8.� FPGA Usage

This chapter discussed the necessary changes required to port the VHDL code to the SRC-6E environment.� The next chapter will discuss benchmarking the SRC-6E, including data collection and analysis.

vI. Data collection and timing analysis

A.�� introduction

This chapter discusses the benchmarks and methods used for collection of data and its analysis during the research.�

b.�� benchmark test platforms

1.�� C Program Executed on a Windows-based Machine

The C program shown in Appendix A was compiled and executed on a 3-GHz Pentium 4 processor system with 2 gigabytes of RAM running the Windows XP Professional operating system.� The primary reason for this benchmark was to draw a comparison for cost-effectiveness between the high-cost special purpose SRC-6E system and a modern, off-the-shelf, general purpose computer.� The same computer that was used for the previous research was used to collect the new data.

2.�� C Program Executed on the SRC-6E

The same C program was compiled and run directly on the SRC-6E without using any of the custom hardware.� Therefore, the data collected is based on the Linux operating system running on a 1-GHz Xeon 3 processor with 1.5 gigabytes of RAM.� Although the system contains dual processors, only one thread is created while running the code and therefore it is believed that only one processor is used during the test.� The primary reason for this benchmark was to test if the algorithm itself is suitable for implementation on the user-logic.

3.�� VHDL Code on the SRC-6E MAP

The VHDL user macro and support files (shown in Appendix C) were built and executed on the SRC-6E MAP.� Two timing data results were collected from each of the runs, the total run time for the entire execution and the time of execution on the MAP only.� The two timing data results compare overhead time to actual execution on the MAP.

c.�� timing data collection method

The data collection method used in this research was identical to the previous work to allow for direct comparison of the results.� The input data sets were composed to represent a stream of intercepted radar samples.� Each data item consists of two hexadecimal characters representing a five-bit intercepted radar sample.� The 32-sample-size data set is shown in Appendix C, which represents the decimal numbers 0 to 31 in order.� All other-sized sample sets were created by duplicating and repeating the same 32 samples in order. By doubling each previous sample set size the following set sizes were created: 32, 64, 128, 256, 512, 1,024, 2,048, 4,096, 8,192, 16,284, 32,786, 65,536, 131,072, and 262,144.� The final set size of 500,000 was chosen as a convenient, large value that was close to the upper array size restriction allowed by the four megabytes of memory per bank on the SRC-6E.

Data from all test platforms were collected in order of increasing input set size.� All raw data used in the timing analysis can be observed in Appendix D.� The timing data was collected by running five consecutive runs of each input data set on each of the three benchmark platforms.� The data for the Windows XP system were collected after a fresh reboot with all unnecessary programs closed.� As noted in the previous research, observation of the system usage during execution of the code again showed that the processor and memory were not fully used, never exceeding 54% usage during the 16-range-bin tests.� The reasons why the processor did not appear to be fully used and the methods Windows uses to measure performance are unknown. �The SRC-6E system data were collected by running the executables on side A when no other users were using the system.

d.�� timing data analysis

1.� Methods

The timing data are displayed in two types of graphs for each range bin size.� The first is the average total time each test platform takes for each data set.� The average is taken of the five data points for each input set size.� The second is the average time per sample for each input set.� First, the average is taken over the five data points and then it is divided by the input set size.� All graphs are connected with straight line approximations between data points.

2.� New Interface Timing Results

Figure 9 shows the SRC MAP call average total time vs. input set size for each of the implemented range bin sizes.��

Figure 9.� Comparison of Average Total Time

The Old 4 Bins plot shows that the new macro interface is more efficient for large input set sizes.� The 4 Bins plot shows a spike at 1024 samples, caused by a single unusually large time result in the data.� The reason for this one slow result is unknown.

3.� 4 Range Bin Timing Results

These results are very similar to those found in the previous research.

Figure 10.� Average Total Time (4 Bins)

Figure 10 shows the average total time for 4 range bins.� All four curves are fairly constant up to the 16,284 sample size.� This result shows that, for small data set sizes, the overhead times inherent in the systems are much greater than the calculation times.� We consider overhead to be all the data file read/write operations and memory accesses required to prepare the data for calculations.� The SRC Macro MAP Call curve clearly shows the calculation time is insignificant compared to the total processing time.

The SRC Macro MAP Call curve also shows the MAP execution time is extremely fast, even for very large data set sizes.� However, the SRC Macro Total curve shows the total execution time for the VHDL macro takes considerably longer.� The extra time represents delays in the system to prepare and transfer the data in and out of the MAP which cause the SRC execution time to be longer for all input set sizes, initially by an order of magnitude.

As the input set size is increased, we see the curves begin to converge.� Figure 11 shows a comparison of the average time per sample.� Figure 12 shows the same data on a semi-log scale.

Figure 11.� Comparison of Average Time per Sample

The overhead in the SRC Macro clearly dominates the graphs for smaller sample set sizes.� However, for larger sample set sizes, the overhead time is amortized over the total time to be nearly insignificant.� The SRC Macro Total time is approaching the other curves and presumably would eventually meet them if the sample set size could be further increased.� However, this is not possible with the current macro design due to the memory design of the SRC-6E hardware.

Figure 12.� Average Time per Sample (4 Bins Semi-Log)

4.� 8 and 16 Range Bin Timing Results

The results for 8 and 16 range bins are similar to 4 range bins.� Figure 13 shows the average total time for 8 range bins.� Figure 14 shows the average total time for 16 bins.� The macros still lack enough parallelism to be effectively implemented on the SRC.� However, it can be observed that the SRC macro time is remaining the same as it was for 4 range bins, while the C program implemented on the Windows XP and SRC are becoming slower.

Figure 13.� Average Total Time(8 Bins)

Figure 14.� Average Total Time(16 Bins)

5.� 64 Range Bin Timing Results

Figure 15 shows the average total time for 64 bins.� For the first time, the SRC macro beats the SRC C program for all sample sizes, demonstrating that the macro implementation is more efficient than the Xeon processor running at 1 GHz.� At 500,000 inputs, the SRC macro also meets the Windows XP C program running at 3 GHz.� Therefore, 64 range bins marks the lower bound for range bin implementation that can be run efficiently on the SRC-6E.

Figure 15.� Average Total Time(64 Bins)

6.� 128 Range Bin Timing Results

Figure 16 shows the average total time for 128 bins.� The SRC macro beats the SRC C program again for all input sizes and by as much as an order of magnitude for large input sizes.� After approximately 50,000 inputs, the SRC macro beats the Windows XP C program.� This clearly demonstrates how a reconfigurable computer which allows the programming of highly specialized hardware for a given problem can be very efficient.

Figure 16.� Average Total Time(128 Bins)

7.� Conclusions

The design of the VHDL macro running on the SRC-6E suffers from excessive overhead which makes it less efficient than the C program which performs the same calculations for implementations below 64 range bins.� Above 64 range bins the macro is very efficient, even beating a Windows XP computer running at a clock speed 30 times higher under certain conditions.

This chapter discussed benchmarking the SRC-6E, including collection of data and analysis, and drew conclusions on the results.� The next chapter draws conclusions on the SRC-6E, including difficulty of use and appropriateness for the chosen algorithm.� Recommendations for future work are also presented.

THIS PAGE INTENTIONALLY LEFT BLANK

VII. conclusions

A.�� introduction

This chapter draws conclusions on the difficulty of use of the SRC-6E, appropriateness of the chosen algorithm for application on the SRC-6E, and gives recommendations for future work.

b.�� difficulty of use

1.�� Necessary Skills

Programming the SRC-6E to use user-defined macros requires knowledge of high-level programming languages, hardware description languages, hardware component design, and synthesizability.� Relatively few people possess all of these skills to use the system effectively without first receiving significant training.� However, programming the system using only high-level languages of C or Fortran is possible which widens the potential user base to many more people.� Much more research needs to be performed to determine if either method produces more effective solutions.

2.�� Experience Level

The SRC-6E has a relatively steep learning curve.� There are a few examples in the documentation and a very small body of work in place using the system.� The errors generated by the system during development are not intuitive and cannot be solved without previous experience with solving the same errors.� The SRC support staff are very helpful in solving specific code problems but are not forthcoming in the reasons or methods used to resolve them.� There are no development tools in place to assist novice users in programming the system.� More research is required to see how much experience on the system is required to prevent and or recognize these types of errors quickly.

3.�� Development Time

The development time to implement solutions on this system appears to be high, primarily due to the steep learning curve and lack of development tools.� This research represents approximately six months of part-time work by a single, moderately experienced person.� More research must be performed to further quantify the development time and see how it improves once a group of experienced repeat users is grown.� No research has yet been performed with large projects, employing multiple programmers, to see if the total project time can be reduced effectively.

c.�� appropriateness of this algorithm for testing

The chosen implementation of the false target radar imaging algorithm appears to be one that would benefit from a reconfigurable computer because it is pipelined and supports parallel processing.� However, implementation of the design with 64 or less range bins has been shown to lack the necessary parallelism required to fully use the hardware and make it effective.� Without increases in the memory size allocated for the user logic, implementation below 64 range bins on the SRC-6E is not an effective solution in terms of development time, processing time, or cost-effectiveness.� Above 64 range bins the algorithm has the required parallelism to make implementation on the SRC-6E worthwhile.

D.�� appropriateness of the SRC-6E for implementation

The SRC-6E user logic is tied to a permanent 100MHz clock which would limit the range resolution if it were used to implement an actual false target radar imaging system.� Range resolution is defined as [10]:

, where C is the speed of light, and �is the clock speed.� With a clock speed of 100 MHz range resolution is 1.5 meters.� Ref [10] reports a system would require at least a 500 MHz clock speed which results in a resolution of 0.3 meters necessary to fool modern radars.� Maximum target size is defined as [10]:

, where �is the number of range bins.

Using 128 range bins results in a maximum target size of 192 meters.� With an expected 200 range bins possible, 300 meters is achievable.� With the use of two user logic areas possible, over 400 range bins should be achievable, resulting in 600 meters.� Future versions of reconfigureable computers using more modern FPGA�s with both larger sizes and faster clock speeds could make a workable false target radar imaging system achievable with this type of technology.

E.�� recommendations for future work

1.�� Develop Implementation of More Range Bins.

The current interface is built to allow scalability to implement any number of range bins in units of 4.� 256 range bins have been shown to be too large to fit within the user logic while 128 range bins fits with 68% usage.� Additional work could be performed to determine the actual upper limit for how many range bins will fit within the user logic area.� It is likely that upwards of 200 range bins could fit.� Also, future research could include using more than one user logic chip to implement twice as many range bins.� No known research to date has been performed which uses both user logic chips on the same MAP simultaneously.

2.�� Develop a More User-Friendly Programming Environment.

As previously discussed, the SRC-6E lacks a custom code editing environment with modern features such as real time syntax checking.� Automated generation of some of the support files could also be implemented.� Project wizards could be created that ask a few questions and then create the skeletons of the support files for the project.� Changes to one file that affect another could be automatically corrected or at a minimum generate warnings.

3.�� Testing Other Applications.

The knowledge base of what types of applications do or do not work efficiently on this system is very small.� Many more algorithms need to be tested on the system.� Programming the same algorithm with both the high level language method and the user macro method would also provide information on which produces better results for different types of algorithms.� Cost and timing comparison to modern, readily available computers should continue to be made.

appendix A

This appendix contains the C code written by Professor Douglas Fouts that was used as a standard for output correctness and as a source of timing data.� Slight modifications were made to provide for timing result output and increased sample sizes.� The version presented was used on both the SRC-6E and the Windows XP platforms for timing analysis with no modifications.

A.�� chip2_sim.c

/* Simulate the DIS-512 chip. */

/* Compile Command */

/* cc Chip2_Sim.c -lm */

/* Range bin phase increment data must be in the file phzinc.txt. */

/* Range bin amplitude scaling data must be in the file ampscal.txt. */

/* Pulse phase samples must be in the file phzsamp.txt. */

/* Output results are put into the file IandQout.txt */

/* Global Included Files */

#include <stdio.h>

#include <math.h>

#include <time.h>

/* Global Defines */

#define rangebins 128�� /* Number of range bins. */

#define phzsamps 500000�� /* Maximum number of phase samples. */

/* Global Data Structures */

int phzincdat[rangebins],�� /* Stores phase increments for each range bin. */

�� ampscaldat[rangebins],�� /* Stores amplitude scaling factors for each range bin. */

�� Ipartres[phzsamps + rangebins][rangebins],�� /* Stores partial results for each phase sample */

�� Qpartres[phzsamps + rangebins][rangebins],�� /*� in each range bin. */

�� sintab[32], costab[32],�� /* Sin and Cos lookup tables. */

�� numofsamps;�� /* Used to count number of samples read in from file phzsamp.txt. */

/* Read in phase increment values for each range bin, */

/* and store the results in the array phzincdat.�� */

rdphzinc()

{

�� /* Local Variables */

�� FILE *filepnt;

�� int rbcnt;

�� /* Open the input file phzinc.txt. */

�� if ((filepnt = fopen("phzinc.txt", "r")) == NULL)

�� fprintf(stderr, "\n\nTERMINAL FAULT:� File phzinc.txt not found.\n\n");

�� /* For each range bin. */

�� for (rbcnt = 0; rbcnt < rangebins; rbcnt++)

�� {

�� fscanf(filepnt, "%x", &phzincdat[rbcnt]);�� /* Read in phase increment value. */

�� }�� /* end of for loop */

�� /* Close input file. */

�� fclose(filepnt);

}�� /* End of function rdphzinc. */

/* Read in amplitude scaling values for each range bin, */

/* and store result in array ampscaldata.�� */

rdampscal()

{

�� /* Local Variables */

�� FILE *filepnt;

�� int rbcnt, inptampdat, tstampdat;

�� /* Open the input file ampscal.txt. */

�� if ((filepnt = fopen("ampscal.txt", "r")) == NULL)

�� fprintf(stderr, "\n\nTERMINAL FAULT:� File ampscal.txt not found.\n\n");

�� /* Read in amplitude scaling values for each range bin. */

�� for (rbcnt = 0; rbcnt < rangebins; rbcnt++)

�� {

�� fscanf(filepnt, "%x", &inptampdat);

�� ampscaldat[rbcnt] = 0x00000001 & inptampdat;

�� tstampdat = 0x00000001 & (inptampdat >> 1);

�� if (tstampdat == 1)

�� ampscaldat[rbcnt] = ampscaldat[rbcnt] + 2;

�� tstampdat = 0x00000001 & (inptampdat >> 2);

�� if (tstampdat == 1)

�� ampscaldat[rbcnt] = ampscaldat[rbcnt] + 3;

�� tstampdat = 0x00000001 & (inptampdat >> 3);

�� if (tstampdat == 1)

�� ampscaldat[rbcnt] = ampscaldat[rbcnt] + 4;

�� }

�� /* Close input file. */

�� fclose(filepnt);

}�� /* End of function rdampscal. */

/* Initialize the global storage arrays. */

initarrays()

{

�� /* Local Variables */

�� int sampnum, rbnum;

�� /* Initialize the partial result array. */

�� for (sampnum = 0; sampnum < phzsamps; sampnum++)

�� for (rbnum = 0; rbnum < rangebins; rbnum++)

�� {

�� Ipartres[sampnum + rbnum][rbnum] = 0;

�� Qpartres[sampnum + rbnum][rbnum] = 0;

�� }

�� /* Initialize the sin table. */

�� sintab[0] = 0x00000000;

�� sintab[1] = 0x00000019;

�� sintab[2] = 0x00000031;

�� sintab[3] = 0x00000047;

�� sintab[4] = 0x0000005A;

�� sintab[5] = 0x0000006A;

�� sintab[6] = 0x00000075;

�� sintab[7] = 0x0000007D;

�� sintab[8] = 0x0000007F;

�� sintab[9] = 0x0000007D;

�� sintab[10] = 0x00000075;

�� sintab[11] = 0x0000006A;

�� sintab[12] = 0x0000005A;

�� sintab[13] = 0x00000047;

�� sintab[14] = 0x00000031;

�� sintab[15] = 0x00000019;

�� sintab[16] = 0x00000000;

�� sintab[17] = 0xFFFFFFE7;

�� sintab[18] = 0xFFFFFFCF;

�� sintab[19] = 0xFFFFFFB9;

�� sintab[20] = 0xFFFFFFA6;

�� sintab[21] = 0xFFFFFF96;

�� sintab[22] = 0xFFFFFF8B;

�� sintab[23] = 0xFFFFFF83;

�� sintab[24] = 0xFFFFFF81;

�� sintab[25] = 0xFFFFFF83;

�� sintab[26] = 0xFFFFFF8B;

�� sintab[27] = 0xFFFFFF96;

�� sintab[28] = 0xFFFFFFA6;

�� sintab[29] = 0xFFFFFFB9;

�� sintab[30] = 0xFFFFFFCF;

�� sintab[31] = 0xFFFFFFE7;

�� /* Initialize the cos table. */

�� costab[0] = 0x0000007F;

�� costab[1] = 0x0000007D;

�� costab[2] = 0x00000075;

�� costab[3] = 0x0000006A;

�� costab[4] = 0x0000005A;

�� costab[5] = 0x00000047;

�� costab[6] = 0x00000031;

�� costab[7] = 0x00000019;

�� costab[8] = 0x00000000;

�� costab[9] = 0xFFFFFFE7;

�� costab[10] = 0xFFFFFFCF;

�� costab[11] = 0xFFFFFFB9;

�� costab[12] = 0xFFFFFFA6;

�� costab[13] = 0xFFFFFF96;

�� costab[14] = 0xFFFFFF8B;

�� costab[15] = 0xFFFFFF83;

�� costab[16] = 0xFFFFFF81;

�� costab[17] = 0xFFFFFF83;

�� costab[18] = 0xFFFFFF8B;

�� costab[19] = 0xFFFFFF96;

�� costab[20] = 0xFFFFFFA6;

�� costab[21] = 0xFFFFFFB9;

�� costab[22] = 0xFFFFFFCF;

�� costab[23] = 0xFFFFFFE7;

� �costab[24] = 0x00000000;

�� costab[25] = 0x00000019;

�� costab[26] = 0x00000031;

�� costab[27] = 0x00000047;

�� costab[28] = 0x0000005A;

�� costab[29] = 0x0000006A;

�� costab[30] = 0x00000075;

�� costab[31] = 0x0000007D;

}�� /* End of function initarrays. */

/* Read in pulse phase samples and calculate partial */

/* results for each range bin and store result in�� */

/* the arrays Ipartres and Qpartres.�� */

rdphzsamp()

{

�� /* Local Variables */

�� FILE *filepnt;

�� int phzdat, phzaddout, ILUTOut, QLUTOut, IGainOut, QGainOut, rbcnt;

�� /* Open the input file phzsamp.txt. */

�� if ((filepnt = fopen("phzsamp.txt", "r")) == NULL)

�� fprintf(stderr, "\n\nTERMINAL FAULT:� File phzsamp.txt not found.\n\n");

�� /* Process each phase sample in the file phzsamp.txt. */

�� numofsamps = 0;

�� while (fscanf(filepnt, "%x", &phzdat) != EOF)

�� {

�� /* Process the new phase sample in each range bin and store the result. */

�� for (rbcnt = 0; rbcnt < rangebins; rbcnt++)

�� {

�� /* Increment the phase. */

�� phzaddout = phzdat + phzincdat[rbcnt];

�� phzaddout = phzaddout & 0x0000001F;

�� /* Calculate I for each range bin and store the result. */

�� ILUTOut = costab[phzaddout];

�� IGainOut = ILUTOut << ampscaldat[rbcnt];

�� if (IGainOut >= 0)

�� IGainOut = IGainOut >> 5;

�� else

�� IGainOut = (IGainOut >> 5) | 0xFFFFE000;

�� IGainOut = IGainOut & 0x0000FFFF;

�� Ipartres[numofsamps + rbcnt][rbcnt] = IGainOut;

�� /* Calculate Q for each range bin and store the result. */

�� QLUTOut = sintab[phzaddout];

�� QGainOut = QLUTOut << ampscaldat[rbcnt];

�� if (QGainOut >= 0)

�� QGainOut = QGainOut >> 5;

�� else

�� QGainOut = (QGainOut >> 5) | 0xFFFFE000;

�� QGainOut = QGainOut & 0x0000FFFF;

�� Qpartres[numofsamps + rbcnt][rbcnt] = QGainOut;

�� }

�� /* Increment the number of phase samples counter. */

�� numofsamps++;

�� }�� /* End of outside while loop. */

�� /* Close input file. */

�� fclose(filepnt);

}�� /* End of function rdphzsamp. */

/* Sum partial results in the array partres and write */

/* final sums to the output file IandQout.txt.�� */

sumpartres()

{

�� /* Local Variables */

�� FILE *filepnt;

�� int sampnum, rbnum, finIout, finQout, IOF, QOF, signofA, signofB, signofsum;

�� /* Open output file for writing. */

�� if ((filepnt = fopen("IandQout.txt", "w")) == NULL)

�� fprintf(stderr, "\n\nTERMINAL FAULT:� File IandQout.txt cannot be written.\n\n");

�� /* put headers in output file */

�� fprintf(filepnt, " I_OF_Out�� Iout�� Q_OF_Out�� Qout\n");

�� fprintf(filepnt, " --------�� ------�� --------�� ------\n\n");

�� /* for all phase samples that were read in */

�� for (sampnum = 0; sampnum < (numofsamps + rangebins - 1); sampnum++)

�� {

�� finIout = finQout = IOF = QOF = 0;�� /* initialize final result */

�� rbnum = rangebins - 1;

�� while (rbnum >= 0)

�� {

�� signofA = (finIout >> 15) & 0x00000001;

�� signofB = (Ipartres[sampnum][rbnum] >> 15) & 0x00000001;

�� finIout = (finIout + Ipartres[sampnum][rbnum]) & 0x0000FFFF;

�� signofsum = (finIout >> 15) & 0x00000001;

�� if ((signofA == 0) && (signofB == 0) && (signofsum == 1))

�� IOF = 1;

�� if ((signofA == 1) && (signofB == 1) && (signofsum == 0))

�� IOF = 1;

�� signofA = (finQout >> 15) & 0x00000001;

�� signofB = (Qpartres[sampnum][rbnum] >> 15) & 0x00000001;

�� finQout = (finQout + Qpartres[sampnum][rbnum]) & 0x0000FFFF;

�� signofsum = (finQout >> 15) & 0x00000001;

�� if ((signofA == 0) && (signofB == 0) && (signofsum == 1))

�� QOF = 1;

�� if ((signofA == 1) && (signofB == 1) && (signofsum == 0))

�� QOF = 1;

�� rbnum--;

�� }

�� /* Print out result to output file. */

�� fprintf(filepnt, "�� %d�� 0x%04X�� %d�� 0x%04X\n", IOF, finIout, QOF, finQout);

�� }�� /* end of outer for loop */

�� /* Close output file. */

�� fclose (filepnt);

}�� /* End of function sumpartres. */

main()

{

�� /* Local Variables */

�� clock_t start, finish;

�� double duration;

�� FILE *filepnt;

�� start=clock();

�� /* Read in phase increment data for each range bin. */

�� rdphzinc();

�� /* Read in amplitude scaling data for each range bin. */

�� rdampscal();

�� /* Initialize global storage arrays. */

�� initarrays();

�� /* Read in pulse phase samples and calculate partial results. */

�� rdphzsamp();

�� /* Sum partial results and output sums. */

�� sumpartres();

�� finish=clock();

�� duration = (double)(finish - start) / CLOCKS_PER_SEC;

�� /* Open output file for writing. */

�� if ((filepnt = fopen("Time.txt", "w")) == NULL)

�� fprintf(stderr, "\n\nTERMINAL FAULT:� File Time.txt cannot be written.\n\n");

�� /* Print out result to output file. */

�� fprintf(filepnt, "Time to complete %i samples: %2.4f seconds.\n", numofsamps, duration);

�� /* Close output file. */

�� fclose (filepnt);

}�� /* End of main. */

Appendix B

This appendix contains the VHDL code that was both tested with Aldec Active-HDL and ported to the SRC-6E.� The full code is shown for the 4 bin version.� Only the changed portion is shown for the other version.� The 4 bin model is labeled to show the section replaced by the other version�s code.

A.�� 4 Bin macro vhdl

------------------------------------------------------------

-- Title�� : FourBin

------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity DFlipFlop is

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit := '1');

end DFLipFlop;��

architecture Equations of DFlipFlop is

begin

process (CLK, LD, RESET)

begin

if CLK='1' and CLK'EVENT then

if� RESET='1' then

Q <= '0';

elsif LD='1' then

Q <= D;

end if;

end process;

Qnot <= not Q;

end Equations;

entity Register5 is

port (CLK,LD,RESET: in bit; D5: in bit_vector (4 downto 0);

�� Q5: inout bit_vector (4 downto 0);

Q5not: out bit_vector (4 downto 0));

end Register5;��

architecture Register5 of Register5 is

component DFlipFlop

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit);

end component;

begin

DFF0: DFlipFlop port map (CLK, LD, RESET, D5(0), Q5(0), Q5not(0));

DFF1: DFlipFlop port map (CLK, LD, RESET, D5(1), Q5(1), Q5not(1));

DFF2: DFlipFlop port map (CLK, LD, RESET, D5(2), Q5(2), Q5not(2));

DFF3: DFlipFlop port map (CLK, LD, RESET, D5(3), Q5(3), Q5not(3));

DFF4: DFlipFlop port map (CLK, LD, RESET, D5(4), Q5(4), Q5not(4));

end Register5;

entity Register8 is

port (CLK, LD, RESET: in bit; D8: in bit_vector (7 downto 0);

Q8: inout bit_vector (7 downto 0);

Q8not: out bit_vector (7 downto 0));

end Register8;

architecture Register8 of Register8 is

component DFlipFlop

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit);

end component;��

begin

DFF0: DFlipFlop port map (CLK, LD, RESET, D8(0), Q8(0), Q8not(0));

DFF1: DFlipFlop port map (CLK, LD, RESET, D8(1), Q8(1), Q8not(1));

DFF2: DFlipFlop port map (CLK, LD, RESET, D8(2), Q8(2), Q8not(2));

DFF3: DFlipFlop port map (CLK, LD, RESET, D8(3), Q8(3), Q8not(3));

DFF4: DFlipFlop port map (CLK, LD, RESET, D8(4), Q8(4), Q8not(4));

DFF5: DFlipFlop port map (CLK, LD, RESET, D8(5), Q8(5), Q8not(5));

DFF6: DFlipFlop port map (CLK, LD, RESET, D8(6), Q8(6), Q8not(6));

DFF7: DFlipFlop port map (CLK, LD, RESET, D8(7), Q8(7), Q8not(7));

end Register8;

entity Register13 is

port (CLK, LD, RESET: in bit; D13: in bit_vector (12 downto 0);

Q13: inout bit_vector (12 downto 0);

Q13not: out bit_vector (12 downto 0));

end Register13;

architecture Register13 of Register13 is

component DFlipFlop

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit);

end component;��

begin

DFF0: DFlipFlop port map (CLK, LD, RESET, D13(0), Q13(0), Q13not(0));

DFF1: DFlipFlop port map (CLK, LD, RESET, D13(1), Q13(1), Q13not(1));

DFF2: DFlipFlop port map (CLK, LD, RESET, D13(2), Q13(2), Q13not(2));

DFF3: DFlipFlop port map (CLK, LD, RESET, D13(3), Q13(3), Q13not(3));

DFF4: DFlipFlop port map (CLK, LD, RESET, D13(4), Q13(4), Q13not(4));

DFF5: DFlipFlop port map (CLK, LD, RESET, D13(5), Q13(5), Q13not(5));

DFF6: DFlipFlop port map (CLK, LD, RESET, D13(6), Q13(6), Q13not(6));

DFF7: DFlipFlop port map (CLK, LD, RESET, D13(7), Q13(7), Q13not(7));�

DFF8: DFlipFlop port map (CLK, LD, RESET, D13(8), Q13(8), Q13not(8));

DFF9: DFlipFlop port map (CLK, LD, RESET, D13(9), Q13(9), Q13not(9));

DFF10: DFlipFlop port map (CLK, LD, RESET, D13(10), Q13(10), Q13not(10));

DFF11: DFlipFlop port map (CLK, LD, RESET, D13(11), Q13(11), Q13not(11));

DFF12: DFlipFlop port map (CLK, LD, RESET, D13(12), Q13(12), Q13not(12));

end Register13;

entity Register17 is

port (CLK, LD, RESET: in bit; D17: in bit_vector (16 downto 0);

Q17: inout bit_vector (16 downto 0);

Q17not: out bit_vector (16 downto 0));

end Register17;

architecture Register17 of Register17 is

component DFlipFlop

port (CLK, LD, RESET,D: in bit;

Q: inout bit; Qnot: out bit);

end component;��

begin

DFF0: DFlipFlop port map (CLK, LD, RESET, D17(0), Q17(0), Q17not(0));

DFF1: DFlipFlop port map (CLK, LD, RESET, D17(1), Q17(1), Q17not(1));

DFF2: DFlipFlop port map (CLK, LD, RESET, D17(2), Q17(2), Q17not(2));

DFF3: DFlipFlop port map (CLK, LD, RESET, D17(3), Q17(3), Q17not(3));

DFF4: DFlipFlop port map (CLK, LD, RESET, D17(4), Q17(4), Q17not(4));

DFF5: DFlipFlop port map (CLK, LD, RESET, D17(5), Q17(5), Q17not(5));

DFF6: DFlipFlop port map (CLK, LD, RESET, D17(6), Q17(6), Q17not(6));

DFF7: DFlipFlop port map (CLK, LD, RESET, D17(7), Q17(7), Q17not(7));�

DFF8: DFlipFlop port map (CLK, LD, RESET, D17(8), Q17(8), Q17not(8));

DFF9: DFlipFlop port map (CLK, LD, RESET, D17(9), Q17(9), Q17not(9));

DFF10: DFlipFlop port map (CLK, LD, RESET, D17(10), Q17(10), Q17not(10));

DFF11: DFlipFlop port map (CLK, LD, RESET, D17(11), Q17(11), Q17not(11));

DFF12: DFlipFlop port map (CLK, LD, RESET, D17(12), Q17(12), Q17not(12));

DFF13: DFlipFlop port map (CLK, LD, RESET, D17(13), Q17(13), Q17not(13));

DFF14: DFlipFlop port map (CLK, LD, RESET, D17(14), Q17(14), Q17not(14));

DFF15: DFlipFlop port map (CLK, LD, RESET, D17(15), Q17(15), Q17not(15));

DFF16: DFlipFlop port map (CLK, LD, RESET, D17(16), Q17(16), Q17not(16));

end Register17;

entity ROMLUT is

port (SIN, COS:out bit_vector(8 downto 1);

� FIVEBITS:in bit_vector(5 downto 1));

end ROMLUT;

architecture ROMLUT of ROMLUT is

signal ROMLUTValue : bit_vector(15 downto 0);

begin

with FIVEBITS Select

�� ROMLUTValue <="0000000001111111" when "00000",--0

"0001100101111101" when "00001",--1

"0011000101110101" when "00010",--2

"0100011101101010" when "00011",--3

"0101101001011010" when "00100",--4

"0110101001000111" when "00101",--5

"0111010100110001" when "00110",--6

"0111110100011001" when "00111",--7

"0111111100000000" when "01000",--8

"0111110111100111" when "01001",--9

"0111010111001111" when "01010",--A

"0110101010111001" when "01011",--b

"0101101010100110" when "01100",--C

"0100011110010110" when "01101",--d

"0011000110001011" when "01110",--E

"0001100110000011" when "01111",--F

"0000000010000001" when "10000",--10

"1110011110000011" when "10001",--11

"1100111110001011" when "10010",--12

"1011100110010110" when "10011",--13

"1010011010100110" when "10100",--14

"1001011010111001" when "10101",--15

"1000101111001111" when "10110",--16

"1000001111100111" when "10111",--17

"1000000100000000" when "11000",--18

"1000001100011001" when "11001",--19

"1000101100110001" when "11010",--1A

"1001011001000111" when "11011",--1b

"1010011001011010" when "11100",--1C

"1011100101101010" when "11101",--1d

"1100111101110101" when "11110",--1E

"1110011101111101" when "11111",--1F

"0000000000000000" when others;--Never Occurs

�

�� SIN <= ROMLUTValue(15 downto 8);

�� COS <= ROMLUTValue(7 downto 0);

end ROMLUT;��

entity FullAdder is��

port (X, Y, Cin: in bit;

Cout, Sum: out bit);

end FullAdder;

architecture Equations of FullAdder is

begin

Sum <= X xor Y xor Cin;

Cout <= (X and Y) or (X and Cin) or (Y and Cin);

end Equations;

entity FullAdderOV is

port (Ci, Cout, OVin: in bit;

� Co, OVout: out bit);

end FullAdderOV;

architecture Equations of FullAdderOV is

begin

Co <= Cout;

OVout <= OVin or (Ci xor Cout);

end Equations;

entity Adder5 is

port (A, B: in bit_vector(4 downto 0); Ci: in bit;

� S: out bit_vector(4 downto 0); Co: out bit);

end Adder5;

architecture Adder5 of Adder5 is

component FullAdder

port (X, Y, Cin: in bit;

Cout, Sum: out bit);

end component;

signal C: bit_vector(4 downto 1);

begin

FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));

FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));

FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));

FA3: FullAdder port map (A(3), B(3), C(3), C(4), S(3));

FA4: FullAdder port map (A(4), B(4), C(4), Co, S(4));

end Adder5;

entity CLAH4 is

port (A, B: in bit_vector(3 downto 0); Cin: in bit;

Cout: out bit);

end CLAH4;

architecture CLAH4 of CLAH4 is

signal g0, g1, g2, g3, p0, p1, p2, p3: bit;

begin

g0 <= A(0) and B(0);

p0 <= A(0) or B(0);

g1 <= A(1) and B(1);

p1 <= A(1) or B(1);

g2 <= A(2) and B(2);

p2 <= A(2) or B(2);

g3 <= A(3) and B(3);

p3 <= A(3) or B(3);

Cout <= g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and g0) or

(p3 and p2 and p1 and p0 and Cin);

end CLAH4;

entity CLAH8 is

port (A, B: in bit_vector(7 downto 0); Cin: in bit;

Cout: out bit);

end CLAH8;

architecture CLAH8 of CLAH8 is

signal g0, g1, g2, g3, g4, g5, g6, g7, p0, p1, p2, p3, p4, p5, p6, p7: bit;

begin

g0 <= A(0) and B(0);

p0 <= A(0) or B(0);

g1 <= A(1) and B(1);

p1 <= A(1) or B(1);

g2 <= A(2) and B(2);

p2 <= A(2) or B(2);

g3 <= A(3) and B(3);

p3 <= A(3) or B(3);

g4 <= A(4) and B(4);

p4 <= A(4) or B(4);

g5 <= A(5) and B(5);

p5 <= A(5) or B(5);

g6 <= A(6) and B(6);

p6 <= A(6) or B(6);

g7 <= A(7) and B(7);

p7 <= A(7) or B(7);��

Cout <= g7 or (p7 and g6) or (p7 and p6 and g5) or (p7 and p6 and p5 and g4) or

(p7 and p6 and p5 and p4 and g3) or

(p7 and p6 and p5 and p4 and p3 and g2) or

(p7 and p6 and p5 and p4 and p3 and p2 and g1) or

(p7 and p6 and p5 and p4 and p3 and p2 and p1 and g0) or

(p7 and p6 and p5 and p4 and p3 and p2 and p1 and p0 and Cin);

end CLAH8;

entity Adder16 is��

port (A, B: in bit_vector(15 downto 0); Ci, OVin: in bit;

� S: out bit_vector(16 downto 0); Co: out bit);

end Adder16; --bit 16 of S is overflow

architecture Adder16 of Adder16 is

component CLAH4

port (A, B: in bit_vector(3 downto 0); Cin: in bit;

Cout: out bit);

end component;

component CLAH8

port (A, B: in bit_vector(7 downto 0); Cin: in bit;

Cout: out bit);

end component;

component FullAdder

port (X, Y, Cin: in bit;

Cout, Sum: out bit);

end component;

component FullAdderOV

port (Ci, Cout, OVin: in bit;

� Co, OVout: out bit);

end component;

signal C: bit_vector(16 downto 1);

signal dummy1, dummy2, dummy3: bit;

begin

FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));

FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));

FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));

FA3: FullAdder port map (A(3), B(3), C(3), dummy1, S(3));

CLAH0: CLAH4 port map (A(3 downto 0), B(3 downto 0), Ci, C(4));

FA4: FullAdder port map (A(4), B(4), C(4), C(5), S(4));

FA5: FullAdder port map (A(5), B(5), C(5), C(6), S(5));

FA6: FullAdder port map (A(6), B(6), C(6), C(7), S(6));

FA7: FullAdder port map (A(7), B(7), C(7), dummy2, S(7));

CLAH1: CLAH8 port map (A(7 downto 0), B(7 downto 0), Ci, C(8));

FA8: FullAdder port map (A(8), B(8), C(8), C(9), S(8));

FA9: FullAdder port map (A(9), B(9), C(9), C(10), S(9));

FA10: FullAdder port map (A(10), B(10), C(10), C(11), S(10));

FA11: FullAdder port map (A(11), B(11), C(11), dummy3, S(11));

CLAH2: CLAH4 port map (A(11 downto 8), B(11 downto 8), C(8), C(12));

FA12: FullAdder port map (A(12), B(12), C(12), C(13), S(12));

FA13: FullAdder port map (A(13), B(13), C(13), C(14), S(13));

FA14: FullAdder port map (A(14), B(14), C(14), C(15), S(14));

FA15: FullAdder port map (A(15), B(15), C(15), C(16), S(15));

FAOV: FullAdderOV port map (C(15), C(16), OVin, Co, S(16));

end Adder16;

entity ControlLogic is

port (ODVin, URB, PSVin, CLK, OPER: in bit;

CLR13, CLR17: out bit := '1'; ODVout, PSVout: out bit);

end ControlLogic;

architecture ControlLogic of ControlLogic is

component DFlipFlop

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit);

end component;��

signal RESET,D1,Q1,Q1Not,D2,Q2,Q2Not,D3,Q3,Q3Not,D4,Q4,Q4Not,

PSVD,PSVQ,PSVQNot:bit;

begin

RESET <= '0';

PSVFF: DFlipFlop port map (CLK, OPER, RESET, PSVD, PSVQ, PSVQNot);

DFF1: DFLipFlop port map(CLK, OPER, RESET, D1, Q1, Q1Not);��

DFF2: DFLipFlop port map(CLK, OPER, RESET, D2, Q2, Q2Not);

DFF3: DFLipFlop port map(CLK, OPER, RESET, D3, Q3, Q3Not);

DFF4: DFLipFlop port map(CLK, OPER, RESET, D4, Q4, Q4Not);

PSVD <= PSVin;

D1 <= URB and PSVQ;

D2 <= Q1;

D3 <= ODVin or Q2;

D4 <= Q3;

CLR13 <= Q2Not;

CLR17 <= Q3Not;

PSVout <= PSVQ;

ODVout <= Q4;

end ControlLogic;

entity GainShifter is

port (Control:in bit_vector(4 downto 1);

Data: in bit_vector(8 downto 1);

Output: out bit_vector(13 downto 1));

end GainShifter;

architecture GainShifter of GainShifter is

begin

process (Control,Data)

begin��

Output(13 downto 1) <= "0000000000000";

case Control is

when "0000" => Output(3 downto 1) <= Data(8 downto 6);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 4) <= "1111111111";

end if;

when "0001" => Output(4 downto 1) <= Data(8 downto 5);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 5) <= "111111111";

end if;

when "0010" => Output(5 downto 1) <= Data(8 downto 4);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 6) <= "11111111";

end if;

when "0011" => Output(6 downto 1) <= Data(8 downto 3);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 7) <= "1111111";

end if;

when "0100" => Output(6 downto 1) <= Data(8 downto 3);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 7) <= "1111111";

end if;

when "0101" => Output(7 downto 1) <= Data(8 downto 2);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 8) <= "111111";

end if;

when "0110" => Output(8 downto 1) <= Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 9) <= "11111";

end if;

when "0111" => Output(9 downto 2) <= Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 10) <= "1111";

end if;

when "1000" => Output(7 downto 1) <= Data(8 downto 2);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 8) <= "111111";

end if;

when "1001" => Output(8 downto 1) <= Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 9) <= "11111";

end if;

when "1010" => Output(9 downto 2) <= Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 10) <= "1111";

end if;

when "1011" => Output(10 downto 3) <= Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 11) <= "111";

end if;

when "1100" => Output(10 downto 3) <=Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 11) <= "111";

end if;

when "1101" => Output(11 downto 4) <=Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13 downto 12) <= "11";

end if;

when "1110" => Output(12 downto 5) <=Data(8 downto 1);

if Data(8)='1' then --need to preserve the sign bit

Output(13) <= '1';

end if;

when "1111" => Output(13 downto 6) <=Data(8 downto 1);

when others => -- summon blue screen of death

end case;

end process;

end GainShifter;

entity OneBin is��

port (PhaseSamp, PhaseInc: in bit_vector (5 downto 1);

Gain: in bit_vector (4 downto 1);

URB, UNP, PRB, ODVin, PSVin: in bit;

OtherBinDataSIN, OtherBinDataCOS: in bit_vector (17 downto 1);

Q, I: out bit_vector (17 downto 1);

ODVout, PSVout: out bit;

DRFM: out bit_vector (5 downto 1);

CLK: in bit);

end OneBin;

architecture OneBin of OneBin is

component Register5 is

port (CLK, LD, RESET: in bit; D5: in bit_vector (4 downto 0);

Q5: inout bit_vector (4 downto 0); Q5not: out bit_vector (4 downto 0));

end component;

component Register8 is

port (CLK, LD, RESET: in bit; D8: in bit_vector (7 downto 0);

Q8: inout bit_vector (7 downto 0); Q8not: out bit_vector (7 downto 0));

end component;

component Register13 is

port (CLK, LD, RESET: in bit; D13: in bit_vector (12 downto 0);

Q13: inout bit_vector(12 downto 0);Q13not:out bit_vector(12 downto 0));

end component;

component Register17 is

port (CLK, LD, RESET: in bit; D17: in bit_vector (16 downto 0);

Q17: inout bit_vector(16 downto 0);Q17not:out bit_vector(16 downto 0));

end component;��

component Adder5 is

port (A, B: in bit_vector(4 downto 0); Ci: in bit;

� S: out bit_vector(4 downto 0); Co: out bit);

end component;

component Adder16 is

port (A, B: in bit_vector(15 downto 0); Ci, OVin: in bit;

� S: out bit_vector(16 downto 0); Co: out bit);

end component;

component ROMLUT is

port (SIN, COS:out bit_vector(1 to 8);

� FIVEBITS:in bit_vector(1 to 5));

end component;

component GainShifter is

port (Control:in bit_vector(4 downto 1);Data:in bit_vector(8 downto 1);

Output: out bit_vector(13 downto 1));

end component;

component ControlLogic is

port (ODVin, URB, PSVin, CLK, OPER: in bit;

� CLR13, CLR17, ODVout, PSVout: out bit);

end component;

signal QOutReg1,QNotOutReg1,QOutReg2,QNotOutReg2,QOutReg3,QNotOutReg3,QOutReg4,QNotOutReg4,

QOutReg5,QNotOutReg5,QOutReg6,QNotOutReg6,OutAdd1: bit_vector (5 downto 1);��

signal QOutReg7,QNotOutReg7,QOutReg8,QNotOutReg8,LUTSIN, LUTCOS: bit_vector (8 downto 1);

signal QOutReg9,QNotOutReg9,QOutReg10,QNotOutReg10, OutShiftSIN, OutShiftCOS: bit_vector (13 downto 1);

signal QOutReg11,QNotOutReg11,QOutReg12,QNotOutReg12,QOutReg13,QNotOutReg13,QOutReg14,QNotOutReg14,

OutAdd2, OutAdd3: bit_vector (17 downto 1);

signal InputAdder2, InputAdder3: bit_vector (16 downto 1);

signal OPER, LD, CLR5, CLR8, CLR13, CLR17, Ci, Co1, Co2, Co3,

Reset_Inact: bit;

signal InReg5: bit_vector (5 downto 1);

begin��

OPER <='1';

CLR5 <= '0';

CLR8 <= '0';

Ci <= '0';

LD <= '1';

Reset_Inact <= '0';

InReg5(4 downto 1) <= Gain (4 downto 1);

InReg5(5) <= URB;

Reg1: Register5 port map(CLK, PRB, CLR5, PhaseInc(5 downto 1),

QOutReg1(5 downto 1), QNotOutReg1(5 downto 1));

Reg2: Register5 port map(CLK, UNP, CLR5, QOutReg1(5 downto 1),

QOutReg2(5 downto 1), QNotOutReg2(5 downto 1));

Reg3: Register5 port map(CLK, LD, CLR5, PhaseSamp(5 downto 1),

QOutReg3(5 downto 1), QNotOutReg3(5 downto 1));

Add1: Adder5 port map (QOutReg2,QOutReg3, Ci, OutAdd1(5 downto 1), Co1);

Reg4: Register5 port map(CLK, LD, CLR5, OutAdd1(5 downto 1),

QOutReg4(5 downto 1), QNotOutReg4(5 downto 1));

LUT: ROMLUT port map (LUTSIN(8 downto 1),LUTCOS(8 downto 1),

QOutReg4(5 downto 1));

Reg5: Register5 port map(CLK, PRB, CLR5, InReg5(5 downto 1),

QOutReg5(5 downto 1), QNotOutReg5(5 downto 1));

Reg6: Register5 port map(CLK, UNP, CLR5, QOutReg5(5 downto 1),

QOutReg6(5 downto 1), QNotOutReg6(5 downto 1));

Reg7: Register8 port map(CLK, LD, CLR8, LUTSIN(8 downto 1),

QOutReg7(8 downto 1), QNotOutReg7(8 downto 1));

Reg8: Register8 port map(CLK, LD, CLR8, LUTCOS(8 downto 1),

QOutReg8(8 downto 1), QNotOutReg8(8 downto 1));

Shift1: GainShifter port map (QOutReg6(4 downto 1), QOutReg7(8 downto 1),OutShiftSIN(13 downto 1));

Shift2: GainShifter port map (QOutReg6(4 downto 1), QOutReg8(8 downto 1),OutShiftCOS(13 downto 1));

Reg9: Register13 port map(CLK, LD, CLR13, OutShiftSIN(13 downto 1), QOutReg9(13 downto 1),QNotOutReg9(13 downto 1));

Reg10: Register13 port map(CLK, LD, CLR13, OutShiftCOS(13 downto 1), QOutReg10(13 downto 1), QNotOutReg10(13 downto 1));��

Reg11: Register17 port map(CLK, LD, Reset_Inact, OtherBinDataSIN(17 downto 1), QOutReg11(17 downto 1), QNotOutReg11(17 downto 1));��

Reg12: Register17 port map(CLK, LD, Reset_Inact, OtherBinDataCOS(17 downto 1), QOutReg12(17 downto 1), QNotOutReg12(17 downto 1));��

Add2: Adder16 port map (InputAdder2, QOutReg11(16 downto 1), Ci, QOutReg11(17), OutAdd2(17 downto 1),Co2);

Add3: Adder16 port map (InputAdder3, QOutReg12(16 downto 1), Ci, QOutReg12(17), OutAdd3(17 downto 1),Co3);

Reg13: Register17 port map(CLK, LD, CLR17, OutAdd2(17 downto 1), QOutReg13(17 downto 1), QNotOutReg13(17 downto 1));

Reg14: Register17 port map(CLK, LD, CLR17, OutAdd3(17 downto 1), QOutReg14(17 downto 1), QNotOutReg14(17 downto 1));

Control: ControlLogic port map (ODVin, QOutReg6(5), PSVin, CLK, OPER, CLR13, CLR17, ODVout, PSVout);

InputAdder2(13 downto 1) <= QOutReg9(13 downto 1);

InputAdder2(14) <= QOutReg9(13);

InputAdder2(15) <= QOutReg9(13);

InputAdder2(16) <= QOutReg9(13);

InputAdder3(13 downto 1) <= QOutReg10(13 downto 1);

InputAdder3(14) <= QOutReg10(13);

InputAdder3(15) <= QOutReg10(13);

InputAdder3(16) <= QOutReg10(13);

DRFM(5 downto 1) <= QOutReg3(5 downto 1);

Q <= QOutReg13;

I <= QOutReg14;

end OneBin;

--**** BEGIN REPLACE HERE *****

entity FourBin is

port (Input: in bit_vector (63 downto 0);

Output:out bit_vector (63 downto 0); CLK: in bit);

end FourBin;

architecture FourBin of FourBin is

component OneBin is

port (PhaseSamp, PhaseInc: in bit_vector (5 downto 1);

Gain: in bit_vector (4 downto 1);

URB, UNP, PRB, ODVin, PSVin: in bit;

OtherBinDataSIN,OtherBinDataCOS:in bit_vector (17 downto 1);

Q, I: out bit_vector (17 downto 1);

ODVout, PSVout: out bit;

DRFM: out bit_vector (5 downto 1);

CLK: in bit);

end component;

signal Q, I, Q1,I1,Q2,I2,Q3,I3: bit_vector (17 downto 1) :="00000000000000000";

signal DRFM0,DRFM1,DRFM2,DRFM3: bit_vector (5 downto 1):="00000";

signal PSVout0,PSVout1,PSVout2,PSVout3: bit:='0';

signal ODVout0,ODVout1,ODVout2,ODVout3: bit:='0';

signal Gain0,Gain1,Gain2,Gain3: bit_vector (4 downto 1):="0000";

signal PhaseInc0,PhaseInc1,PhaseInc2,PhaseInc3: bit_vector (5 downto 1) :="00000";

signal URB0,URB1,URB2,URB3: bit :='0';

signal PhaseSamp: bit_vector (5 downto 1):= "00000";

signal PRB, UNP, PSVin, ODVin: bit :='0';

begin -- BIN0 is the primary output

--Input: formats, cycle begins when PRB=1, 1 format per clock

-- ten bits of each bin: 10 |� 9-5�� |4-1 |

--�� URB|PhaseInc|Gain|

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin3 | bin2 | bin1 | bin0 |sample |PSVin |UNP |PRB

-- 63-8�� | 7-3�� | 2�� | 1� | 0

--unused�� |sample |PSVin |UNP |PRB

-- The first sample can be entered on clock 2 if PSVin and UNP are taken high

PRB<=Input(0);

UNP<=Input(1);

PSVin<=Input(2);

PhaseSamp<=Input(7 downto 3);

-- Bin 0 data

URB0<=Input(17);

PhaseInc0<=Input(16 downto 12);

Gain0<=Input(11 downto 8);

-- Bin 1 Data

URB1<=Input(27);

PhaseInc1<=Input(26 downto 22);

Gain1<=Input(21 downto 18);��

-- Bin 2 data

URB2<=Input(37);

PhaseInc2<=Input(36 downto 32);

Gain2<=Input(31 downto 28);

-- Bins 3 data

URB3<=Input(47);

PhaseInc3<=Input(46 downto 42);

Gain3<=Input(41 downto 38);

��

BIN0: OneBin port map (DRFM1, PhaseInc0, Gain0, URB0, UNP, PRB, ODVout1, PSVout1, Q1, I1, Q, I, ODVout0, PSVout0, DRFM0, CLK);

BIN1: OneBin port map (DRFM2, PhaseInc1, Gain1, URB1, UNP, PRB, ODVout2, PSVout2, Q2, I2, Q1, I1, ODVout1, PSVout1, DRFM1, CLK);

BIN2: OneBin port map (DRFM3, PhaseInc2, Gain2, URB2, UNP, PRB, ODVout3, PSVout3, Q3, I3, Q2, I2, ODVout2, PSVout2, DRFM2, CLK);

BIN3: OneBin port map (PhaseSamp, PhaseInc3, Gain3, URB3, UNP, PRB, ODVin, PSVin, "00000000000000000", "00000000000000000", Q3, I3,

ODVout3, PSVout3, DRFM3, CLK);

-- Output Format:

-- 63-41 |�� 40�� |�� 39�� | 38-22 | 21-5 | 4-0

�

Output(40)<=PSVout0;

Output(39)<=ODVout0;

Output(38 downto 22)<=Q;

Output(21 downto 5)<=I;

Output(4 downto 0)<=DRFM0;

Output(63 downto 41)<="00000000000000000000000";

end FourBin;

--**** END REPLACE HERE *****

B.�� 8 Bin macro vhdl

entity EightBin is

port (Input: in bit_vector (63 downto 0);

Output:out bit_vector (63 downto 0); CLK: in bit);

end EightBin;

architecture EightBin of EightBin is

component OneBin is

port (PhaseSamp, PhaseInc: in bit_vector (5 downto 1);

Gain: in bit_vector (4 downto 1);

URB, UNP, PRB, ODVin, PSVin: in bit;

OtherBinDataSIN,OtherBinDataCOS:in bit_vector (17 downto 1);

Q, I: out bit_vector (17 downto 1);

ODVout, PSVout: out bit;

DRFM: out bit_vector (5 downto 1);

CLK: in bit);

end component;

component DFlipFlop

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit);

end component;

signal Q, I, Q1,I1,Q2,I2,Q3,I3,Q4,I4,Q5,I5,Q6,I6,Q7,I7: bit_vector (17 downto 1):="00000000000000000";

signal DRFM0,DRFM1,DRFM2,DRFM3,DRFM4,DRFM5,DRFM6,DRFM7: bit_vector (5 downto 1):="00000";

signal PSVout0,PSVout1,PSVout2,PSVout3,PSVout4,PSVout5,PSVout6,PSVout7: bit:='0';

signal ODVout0,ODVout1,ODVout2,ODVout3,ODVout4,ODVout5,ODVout6,ODVout7: bit:='0';

signal Gain0,Gain1,Gain2,Gain3,Gain4,Gain5,Gain6,Gain7: bit_vector (4 downto 1):="0000";

signal PhaseInc0,PhaseInc1,PhaseInc2,PhaseInc3,PhaseInc4,

PhaseInc5,PhaseInc6,PhaseInc7 : bit_vector (5 downto 1):="00000";

signal URB0,URB1,URB2,URB3,URB4,URB5,URB6,URB7: bit :='0';

signal PhaseSamp: bit_vector (5 downto 1):= "00000";

signal UNP, PSVin, ODVin: bit :='0';

signal LD, RESET, PRB, PRB1, PRB1not: bit;

begin -- BIN0 is the primary output

--Input: formats, cycle begins when PRB=1, 1 format per clock

-- ten bits of each bin: 10 |� 9-5�� |4-1 |

--�� URB|PhaseInc|Gain|

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin3 | bin2 | bin1 | bin0 |sample |PSVin |UNP |PRB

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin7 | bin6 | bin5 | bin4 |sample |PSVin |UNP |PRB

-- 63-8�� | 7-3�� | 2�� | 1� | 0

--unused�� |sample |PSVin |UNP |PRB

-- The first sample can be entered on clock 3 if PSVin and UNP are taken high

LD<='1';

RESET<='0';

PRB<=Input(0);

UNP<=Input(1);

PSVin<=Input(2);

PhaseSamp<=Input(7 downto 3);

-- Bins 0,4 data

URB0<=Input(17);

PhaseInc0<=Input(16 downto 12);

Gain0<=Input(11 downto 8);

URB4<=Input(17);

PhaseInc4<=Input(16 downto 12);

Gain4<=Input(11 downto 8);

-- Bins 1,5 data

URB1<=Input(27);

PhaseInc1<=Input(26 downto 22);

Gain1<=Input(21 downto 18);��

URB5<=Input(27);

PhaseInc5<=Input(26 downto 22);

Gain5<=Input(21 downto 18);

-- Bins 2,6 data

URB2<=Input(37);

PhaseInc2<=Input(36 downto 32);

Gain2<=Input(31 downto 28);

URB6<=Input(37);

PhaseInc6<=Input(36 downto 32);

Gain6<=Input(31 downto 28);

-- Bins 3,7 data

URB3<=Input(47);

PhaseInc3<=Input(46 downto 42);

Gain3<=Input(41 downto 38);

URB7<=Input(47);

PhaseInc7<=Input(46 downto 42);

Gain7<=Input(41 downto 38);

��

DFF: DFlipFlop port map (CLK, LD, RESET, PRB, PRB1, PRB1not);

BIN0: OneBin port map (DRFM1, PhaseInc0, Gain0, URB0, UNP, PRB, ODVout1, PSVout1, Q1, I1, Q, I, ODVout0, PSVout0, DRFM0, CLK);

BIN1: OneBin port map (DRFM2, PhaseInc1, Gain1, URB1, UNP, PRB, ODVout2, PSVout2, Q2, I2, Q1, I1, ODVout1, PSVout1, DRFM1, CLK);

BIN2: OneBin port map (DRFM3, PhaseInc2, Gain2, URB2, UNP, PRB, ODVout3, PSVout3, Q3, I3, Q2, I2, ODVout2, PSVout2, DRFM2, CLK);

BIN3: OneBin port map (DRFM4, PhaseInc3, Gain3, URB3, UNP, PRB, ODVout4, PSVout4, Q4, I4, Q3, I3, ODVout3, PSVout3, DRFM3, CLK);

BIN4: OneBin port map (DRFM5, PhaseInc4, Gain4, URB4, UNP, PRB1, ODVout5, PSVout5, Q5, I5, Q4, I4, ODVout4, PSVout4, DRFM4, CLK);

BIN5: OneBin port map (DRFM6, PhaseInc5, Gain5, URB5, UNP, PRB1, ODVout6, PSVout6, Q6, I6, Q5, I5, ODVout5, PSVout5, DRFM5, CLK);

BIN6: OneBin port map (DRFM7, PhaseInc6, Gain6, URB6, UNP, PRB1, ODVout7, PSVout7, Q7, I7, Q6, I6, ODVout6, PSVout6, DRFM6, CLK);

BIN7: OneBin port map (PhaseSamp, PhaseInc7, Gain7, URB7, UNP, PRB1, ODVin, PSVin, "00000000000000000", "00000000000000000", Q7, I7,

ODVout7, PSVout7, DRFM7, CLK);

-- Output Format:

-- 63-41 |� �40�� |�� 39�� | 38-22 | 21-5 | 4-0

�

Output(40)<=PSVout0;

Output(39)<=ODVout0;

Output(38 downto 22)<=Q;

Output(21 downto 5)<=I;

Output(4 downto 0)<=DRFM0;

Output(63 downto 41)<="00000000000000000000000";

end EightBin;

C.�� 16 Bin macro vhdl

entity SixteenBin is

port (Input: in bit_vector (63 downto 0);

Output:out bit_vector (63 downto 0); CLK: in bit);

end SixteenBin;

architecture SixteenBin of SixteenBin is

component OneBin is

port (PhaseSamp, PhaseInc: in bit_vector (5 downto 1);

Gain: in bit_vector (4 downto 1);

URB, UNP, PRB, ODVin, PSVin: in bit;

OtherBinDataSIN,OtherBinDataCOS:in bit_vector (17 downto 1);

Q, I: out bit_vector (17 downto 1);

ODVout, PSVout: out bit;

DRFM: out bit_vector (5 downto 1);

CLK: in bit);

end component;

component DFlipFlop

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit);

end component;��

signal Q, I, Q1,I1,Q2,I2,Q3,I3,Q4,I4,Q5,I5,Q6,I6,Q7,I7,Q8,I8,Q9,I9,

Q10,I10,Q11,I11,Q12,I12,Q13,I13,Q14,I14, Q15,I15: bit_vector (17 downto 1):="00000000000000000";

signal DRFM0,DRFM1,DRFM2,DRFM3,DRFM4,DRFM5,DRFM6,DRFM7,DRFM8,DRFM9,

DRFM10,DRFM11,DRFM12,DRFM13,DRFM14,DRFM15: bit_vector (5 downto 1):="00000";

signal PSVout0,PSVout1,PSVout2,PSVout3,PSVout4,PSVout5,PSVout6,

PSVout7,PSVout8,PSVout9,PSVout10,PSVout11,PSVout12,PSVout13,PSVout14,PSVout15: bit:='0';

signal ODVout0,ODVout1,ODVout2,ODVout3,ODVout4,ODVout5,ODVout6,

ODVout7,ODVout8,ODVout9,ODVout10,ODVout11,ODVout12,ODVout13,ODVout14,ODVout15: bit:='0';

signal Gain0,Gain1,Gain2,Gain3,Gain4,Gain5,Gain6,Gain7,Gain8,Gain9,

Gain10,Gain11,Gain12,Gain13,Gain14,Gain15: bit_vector (4 downto 1):="0000";

Signal PhaseInc0,PhaseInc1,PhaseInc2,PhaseInc3,PhaseInc4,PhaseInc5,PhaseInc6,

PhaseInc7 : bit_vector (5 downto 1):="00000";

signal PhaseInc8,PhaseInc9,PhaseInc10,PhaseInc11,PhaseInc12,PhaseInc13,

PhaseInc14,PhaseInc15 : bit_vector (5 downto 1):="00000";

signal URB0,URB1,URB2,URB3,URB4,URB5,URB6,URB7,URB8,URB9,URB10,URB11,

URB12,URB13,URB14,URB15: bit :='0';

signal PhaseSamp: bit_vector (5 downto 1):= "00000";

signal UNP, PSVin, ODVin: bit :='0';

signal LD, RESET, PRB, PRB1, PRB2, PRB3, PRB1not,PRB2not,PRB3not: bit;

begin -- BIN0 is the primary output

--Input: formats, cycle begins when PRB=1, 1 format per clock

-- ten bits of each bin: 10 |� 9-5�� |4-1 |

--�� URB|PhaseInc|Gain|

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin3 | bin2 | bin1 | bin0 |sample |PSVin |UNP |PRB

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin7 | bin6 | bin5 | bin4 |sample |PSVin |UNP |PRB

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin11| bin10| bin9 | bin8 |sample |PSVin |UNP |PRB

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin15| bin14| bin13| bin12|sample |PSVin |UNP |PRB

-- 63-8�� | 7-3�� | 2�� | 1� | 0

--unused�� |sample |PSVin |UNP |PRB

-- The first sample can be entered on clock 5 if PSVin and UNP are taken high

LD<='1';

RESET<='0';

PRB<=Input(0);

UNP<=Input(1);

PSVin<=Input(2);

PhaseSamp<=Input(7 downto 3);

-- Bins 0,4,8,12 data

URB0<=Input(17);

PhaseInc0<=Input(16 downto 12);

Gain0<=Input(11 downto 8);

URB4<=Input(17);

PhaseInc4<=Input(16 downto 12);

Gain4<=Input(11 downto 8);

URB8<=Input(17);

PhaseInc8<=Input(16 downto 12);

Gain8<=Input(11 downto 8);

URB12<=Input(17);

PhaseInc12<=Input(16 downto 12);

Gain12<=Input(11 downto 8);

-- Bins 1,5,9,13 data

URB1<=Input(27);

PhaseInc1<=Input(26 downto 22);

Gain1<=Input(21 downto 18);��

URB5<=Input(27);

PhaseInc5<=Input(26 downto 22);

Gain5<=Input(21 downto 18);

URB9<=Input(27);

PhaseInc9<=Input(26 downto 22);

Gain9<=Input(21 downto 18);

URB13<=Input(27);

PhaseInc13<=Input(26 downto 22);

Gain13<=Input(21 downto 18);

-- Bins 2,6,10,14 data

URB2<=Input(37);

PhaseInc2<=Input(36 downto 32);

Gain2<=Input(31 downto 28);

URB6<=Input(37);

PhaseInc6<=Input(36 downto 32);

Gain6<=Input(31 downto 28);

URB10<=Input(37);

PhaseInc10<=Input(36 downto 32);

Gain10<=Input(31 downto 28);

URB14<=Input(37);

PhaseInc14<=Input(36 downto 32);

Gain14<=Input(31 downto 28);

-- Bins 3,7,11,15 data

URB3<=Input(47);

PhaseInc3<=Input(46 downto 42);

Gain3<=Input(41 downto 38);

URB7<=Input(47);

PhaseInc7<=Input(46 downto 42);

Gain7<=Input(41 downto 38);

URB11<=Input(47);

PhaseInc11<=Input(46 downto 42);

Gain11<=Input(41 downto 38);

URB15<=Input(47);

PhaseInc15<=Input(46 downto 42);

Gain15<=Input(41 downto 38);

��

DFF0: DFlipFlop port map (CLK, LD, RESET, PRB, PRB1, PRB1not);

DFF1: DFlipFlop port map (CLK, LD, RESET, PRB1, PRB2, PRB2not);

DFF2: DFlipFlop port map (CLK, LD, RESET, PRB2, PRB3, PRB3not);

BIN0: OneBin port map (DRFM1, PhaseInc0, Gain0, URB0, UNP, PRB, ODVout1, PSVout1, Q1, I1, Q, I, ODVout0, PSVout0, DRFM0, CLK);

BIN1: OneBin port map (DRFM2, PhaseInc1, Gain1, URB1, UNP, PRB, ODVout2, PSVout2, Q2, I2, Q1, I1, ODVout1, PSVout1, DRFM1, CLK);

BIN2: OneBin port map (DRFM3, PhaseInc2, Gain2, URB2, UNP, PRB, ODVout3, PSVout3, Q3, I3, Q2, I2, ODVout2, PSVout2, DRFM2, CLK);

BIN3: OneBin port map (DRFM4, PhaseInc3, Gain3, URB3, UNP, PRB, ODVout4, PSVout4, Q4, I4, Q3, I3, ODVout3, PSVout3, DRFM3, CLK);

BIN4: OneBin port map (DRFM5, PhaseInc4, Gain4, URB4, UNP, PRB1, ODVout5, PSVout5, Q5, I5, Q4, I4, ODVout4, PSVout4, DRFM4, CLK);

BIN5: OneBin port map (DRFM6, PhaseInc5, Gain5, URB5, UNP, PRB1, ODVout6, PSVout6, Q6, I6, Q5, I5, ODVout5, PSVout5, DRFM5, CLK);

BIN6: OneBin port map (DRFM7, PhaseInc6, Gain6, URB6, UNP, PRB1, ODVout7, PSVout7, Q7, I7, Q6, I6, ODVout6, PSVout6, DRFM6, CLK);

BIN7: OneBin port map (DRFM8, PhaseInc7, Gain7, URB7, UNP, PRB1, ODVout8, PSVout8, Q8, I8, Q7, I7, ODVout7, PSVout7, DRFM7, CLK);

BIN8: OneBin port map (DRFM9, PhaseInc8, Gain8, URB8, UNP, PRB2, ODVout9, PSVout9, Q9, I9, Q8, I8, ODVout8, PSVout8, DRFM8, CLK);

BIN9: OneBin port map (DRFM10, PhaseInc9, Gain9, URB9, UNP, PRB2, ODVout10, PSVout10, Q10, I10, Q9, I9, ODVout9, PSVout9, DRFM9, CLK);

BIN10: OneBin port map (DRFM11, PhaseInc10, Gain10, URB10, UNP, PRB2, ODVout11, PSVout11, Q11, I11, Q10, I10, ODVout10, PSVout10, DRFM10, CLK);

BIN11: OneBin port map (DRFM12, PhaseInc11, Gain11, URB11, UNP, PRB2, ODVout12, PSVout12, Q12, I12, Q11, I11, ODVout11, PSVout11, DRFM11, CLK);

BIN12: OneBin port map (DRFM13, PhaseInc12, Gain12, URB12, UNP, PRB3, ODVout13, PSVout13, Q13, I13, Q12, I12, ODVout12, PSVout12, DRFM12, CLK);

BIN13: OneBin port map (DRFM14, PhaseInc13, Gain13, URB13, UNP, PRB3, ODVout14, PSVout14, Q14, I14, Q13, I13, ODVout13, PSVout13, DRFM13, CLK);

BIN14: OneBin port map (DRFM15, PhaseInc14, Gain14, URB14, UNP, PRB3, ODVout15, PSVout15, Q15, I15, Q14, I14, ODVout14, PSVout14, DRFM14, CLK);

BIN15: OneBin port map (PhaseSamp, PhaseInc15, Gain15, URB15, UNP, PRB3, ODVin, PSVin, "00000000000000000", "00000000000000000", Q15, I15,

ODVout15, PSVout15, DRFM15, CLK);

��

-- Output Format:

-- 63-41 |�� 40�� |� �39�� | 38-22 | 21-5 | 4-0

�

Output(40)<=PSVout0;

Output(39)<=ODVout0;

Output(38 downto 22)<=Q;

Output(21 downto 5)<=I;

Output(4 downto 0)<=DRFM0;

Output(63 downto 41)<="00000000000000000000000";

end SixteenBin;

D.�� 64 Bin macro vhdl

entity SixtyFourBin is

port (Input: in bit_vector (63 downto 0);

Output:out bit_vector (63 downto 0); CLK: in bit);

end SixtyFourBin;

architecture SixtyFourBin of SixtyFourBin is

component OneBin is

port (PhaseSamp, PhaseInc: in bit_vector (5 downto 1);

Gain: in bit_vector (4 downto 1);

URB, UNP, PRB, ODVin, PSVin: in bit;

OtherBinDataSIN,OtherBinDataCOS:in bit_vector (17 downto 1);

Q, I: out bit_vector (17 downto 1);

ODVout, PSVout: out bit;

DRFM: out bit_vector (5 downto 1);

CLK: in bit);

end component;

component DFlipFlop

port (CLK, LD, RESET, D: in bit;

Q: inout bit; Qnot: out bit);

end component;��

signal Q, I, Q1,I1,Q2,I2,Q3,I3,Q4,I4,Q5,I5,Q6,I6,Q7,I7,Q8,I8,Q9,I9,

Q10,I10,Q11,I11,Q12,I12,Q13,I13,Q14,I14,Q15,I15: bit_vector (17 downto 1):="00000000000000000";

signal Q16, I16, Q17,I17,Q18,I18,Q19,I19,Q20,I20,Q21,I21,Q22,I22,Q23, I23,Q24,I24,Q25,I25,

Q26,I26,Q27,I27,Q28,I28,Q29,I29,Q30,I30,Q31,I31:bit_vector (17 downto 1):="00000000000000000";

signal Q32, I32, Q33,I33,Q34,I34,Q35,I35,Q36,I36,Q37,I37,Q38,I38, Q39,I39,Q40,I40,Q41,I41,

Q42,I42,Q43,I43,Q44,I44,Q45,I45,Q46,I46,Q47,I47: bit_vector (17 downto 1):="00000000000000000";

signal Q48, I48, Q49,I49,Q50,I50,Q51,I51,Q52,I52,Q53,I53,Q54,I54,Q55, I55,Q56,I56,Q57,I57,

Q58,I58,Q59,I59,Q60,I60,Q61,I61,Q62,I62,Q63,I63: bit_vector (17 downto 1):="00000000000000000";

signal DRFM0,DRFM1,DRFM2,DRFM3,DRFM4,DRFM5,DRFM6,DRFM7,DRFM8,DRFM9,

DRFM10,DRFM11,DRFM12,DRFM13,DRFM14,DRFM15: bit_vector (5 downto 1):="00000";

signal DRFM16,DRFM17,DRFM18,DRFM19,DRFM20,DRFM21,DRFM22,DRFM23,DRFM24,DRFM25,

DRFM26,DRFM27,DRFM28,DRFM29,DRFM30,DRFM31: bit_vector (5 downto 1):="00000";

signal DRFM32,DRFM33,DRFM34,DRFM35,DRFM36,DRFM37,DRFM38,DRFM39,DRFM40,DRFM41,

DRFM42,DRFM43,DRFM44,DRFM45,DRFM46,DRFM47: bit_vector (5 downto 1):="00000";

signal DRFM48,DRFM49,DRFM50,DRFM51,DRFM52,DRFM53,DRFM54,DRFM55,DRFM56,DRFM57,

DRFM58,DRFM59,DRFM60,DRFM61,DRFM62,DRFM63: bit_vector (5 downto 1):="00000";

signal PSVout0,PSVout1,PSVout2,PSVout3,PSVout4,PSVout5,PSVout6,

PSVout7,PSVout8,PSVout9,PSVout10,PSVout11,PSVout12,PSVout13,PSVout14, PSVout15: bit:='0';

signal PSVout16,PSVout17,PSVout18,PSVout19,PSVout20,PSVout21,PSVout22,

PSVout23,PSVout24,PSVout25,PSVout26,PSVout27,PSVout28,PSVout29,PSVout30,PSVout31: bit:='0';

signal PSVout32,PSVout33,PSVout34,PSVout35,PSVout36,PSVout37,PSVout38,

PSVout39,PSVout40,PSVout41,PSVout42,PSVout43,PSVout44,PSVout45,PSVout46,PSVout47: bit:='0';

signal PSVout48,PSVout49,PSVout50,PSVout51,PSVout52,PSVout53,PSVout54,

PSVout55,PSVout56,PSVout57,PSVout58,PSVout59,PSVout60,PSVout61,PSVout62,PSVout63: bit:='0';

signal ODVout0,ODVout1,ODVout2,ODVout3,ODVout4,ODVout5,ODVout6,

ODVout7,ODVout8,ODVout9,ODVout10,ODVout11,ODVout12,ODVout13,ODVout14,ODVout15: bit:='0';

signal ODVout16,ODVout17,ODVout18,ODVout19,ODVout20,ODVout21,ODVout22,

ODVout23,ODVout24,ODVout25,ODVout26,ODVout27,ODVout28,ODVout29,ODVout30,ODVout31: bit:='0';

signal ODVout32,ODVout33,ODVout34,ODVout35,ODVout36,ODVout37,ODVout38,

ODVout39,ODVout40,ODVout41,ODVout42,ODVout43,ODVout44,ODVout45,ODVout46,ODVout47: bit:='0';

signal ODVout48,ODVout49,ODVout50,ODVout51,ODVout52,ODVout53,ODVout54,

ODVout55,ODVout56,ODVout57,ODVout58,ODVout59,ODVout60,ODVout61,ODVout62,ODVout63: bit:='0';

signal Gain0,Gain1,Gain2,Gain3,Gain4,Gain5,Gain6,Gain7,Gain8,Gain9,

Gain10,Gain11,Gain12,Gain13,Gain14,Gain15: bit_vector (4 downto 1):="0000";

signal Gain16,Gain17,Gain18,Gain19,Gain20,Gain21,Gain22,Gain23,Gain24,Gain25,

Gain26,Gain27,Gain28,Gain29,Gain30,Gain31: bit_vector (4 downto 1):="0000";

signal Gain32,Gain33,Gain34,Gain35,Gain36,Gain37,Gain38,Gain39,Gain40,Gain41,

Gain42,Gain43,Gain44,Gain45,Gain46,Gain47: bit_vector (4 downto 1):="0000";

signal Gain48,Gain49,Gain50,Gain51,Gain52,Gain53,Gain54,Gain55,Gain56,Gain57,

Gain58,Gain59,Gain60,Gain61,Gain62,Gain63: bit_vector (4 downto 1):="0000";

signal PhaseInc0,PhaseInc1,PhaseInc2,PhaseInc3,PhaseInc4,PhaseInc5,PhaseInc6, PhaseInc7,

PhaseInc8,PhaseInc9,PhaseInc10,PhaseInc11,PhaseInc12,PhaseInc13,PhaseInc14,PhaseInc15 : bit_vector (5 downto 1):="00000";

Signal PhaseInc16,PhaseInc17,PhaseInc18,PhaseInc19,PhaseInc20,PhaseInc21, PhaseInc22,PhaseInc23,

PhaseInc24,PhaseInc25,PhaseInc26,PhaseInc27,PhaseInc28,PhaseInc29,PhaseInc30,PhaseInc31 : bit_vector (5 downto 1):="00000";

signal PhaseInc32,PhaseInc33,PhaseInc34,PhaseInc35,PhaseInc36,PhaseInc37,PhaseInc38,PhaseInc39,

PhaseInc40,PhaseInc41,PhaseInc42,PhaseInc43,PhaseInc44,PhaseInc45,PhaseInc46,PhaseInc47 : bit_vector (5 downto 1):="00000";

signal PhaseInc48,PhaseInc49,PhaseInc50,PhaseInc51,PhaseInc52,PhaseInc53,PhaseInc54,PhaseInc55,

PhaseInc56,PhaseInc57,PhaseInc58,PhaseInc59,PhaseInc60,PhaseInc61,PhaseInc62,PhaseInc63 : bit_vector (5 downto 1):="00000";

signal URB0,URB1,URB2,URB3,URB4,URB5,URB6,URB7,URB8,URB9,URB10,URB11,URB12,URB13,URB14,URB15: bit :='0';

signal URB16,URB17,URB18,URB19,URB20,URB21,URB22,URB23,URB24,URB25,URB26,URB27,URB28,URB29,URB30,URB31: bit :='0';

signal URB32,URB33,URB34,URB35,URB36,URB37,URB38,URB39,URB40,URB41,URB42,URB43,URB44,URB45,URB46,URB47: bit :='0';

signal URB48,URB49,URB50,URB51,URB52,URB53,URB54,URB55,URB56,URB57,URB58,URB59,URB60,URB61,URB62,URB63: bit :='0';

signal PhaseSamp: bit_vector (5 downto 1):= "00000";

signal UNP, PSVin, ODVin: bit :='0';

signal LD, RESET, PRB, PRB1, PRB2, PRB3, PRB4, PRB5, PRB6, PRB7, PRB8, PRB9, PRB10, PRB11, PRB12, PRB13, PRB14, PRB15,

PRB1not,PRB2not,PRB3not,PRB4not,PRB5not,PRB6not,PRB7not,PRB8not,PRB9not,PRB10not,PRB11not,PRB12not,PRB13not,PRB14not,PRB15not: bit;

Begin -- BIN0 is the primary output

--Input: formats, cycle begins when PRB=1, 1 format per clock

-- ten bits of each bin: 10 |� 9-5�� |4-1 |

--�� URB|PhaseInc|Gain|

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin3 | bin2 | bin1 | bin0 |sample |PSVin |UNP |PRB

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin7 | bin6 | bin5 | bin4 |sample |PSVin |UNP |PRB

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin11| bin10| bin9 | bin8 |sample |PSVin |UNP |PRB

-- 63-48 |47-38 |37-28 |27-18 | 17-8 | 7-3�� | 2�� | 1� | 0

--unused | bin15| bin14| bin13| bin12|sample |PSVin |UNP |PRB

-- 63-8�� | 7-3�� | 2�� | 1� | 0

--unused�� |sample |PSVin |UNP |PRB

-- more bins in same pattern up to 63...

-- The first sample can be entered on clock 65 if PSVin and UNP are taken high

LD<='1';

RESET<='0';

PRB<=Input(0);

UNP<=Input(1);

PSVin<=Input(2);

PhaseSamp<=Input(7 downto 3);

-- Bins 0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60 data

URB0<=Input(17);

PhaseInc0<=Input(16 downto 12);

Gain0<=Input(11 downto 8);

URB4<=Input(17);

PhaseInc4<=Input(16 downto 12);

Gain4<=Input(11 downto 8);

URB8<=Input(17);

PhaseInc8<=Input(16 downto 12);

Gain8<=Input(11 downto 8);

URB12<=Input(17);

PhaseInc12<=Input(16 downto 12);

Gain12<=Input(11 downto 8);

URB16<=Input(17);

PhaseInc16<=Input(16 downto 12);

Gain16<=Input(11 downto 8);

URB20<=Input(17);

PhaseInc20<=Input(16 downto 12);

Gain20<=Input(11 downto 8);

URB24<=Input(17);

PhaseInc24<=Input(16 downto 12);

Gain24<=Input(11 downto 8);

URB28<=Input(17);

PhaseInc28<=Input(16 downto 12);

Gain28<=Input(11 downto 8);

URB32<=Input(17);

PhaseInc32<=Input(16 downto 12);

Gain32<=Input(11 downto 8);

URB36<=Input(17);

PhaseInc36<=Input(16 downto 12);

Gain36<=Input(11 downto 8);

URB40<=Input(17);

PhaseInc40<=Input(16 downto 12);

Gain40<=Input(11 downto 8);

URB44<=Input(17);

PhaseInc44<=Input(16 downto 12);

Gain44<=Input(11 downto 8);

URB48<=Input(17);

PhaseInc48<=Input(16 downto 12);

Gain48<=Input(11 downto 8);

URB52<=Input(17);

PhaseInc52<=Input(16 downto 12);

Gain52<=Input(11 downto 8);

URB56<=Input(17);

PhaseInc56<=Input(16 downto 12);

Gain56<=Input(11 downto 8);

URB60<=Input(17);

PhaseInc60<=Input(16 downto 12);

Gain60<=Input(11 downto 8);

-- Bins 1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61� data

URB1<=Input(27);

PhaseInc1<=Input(26 downto 22);

Gain1<=Input(21 downto 18);��

URB5<=Input(27);

PhaseInc5<=Input(26 downto 22);

Gain5<=Input(21 downto 18);

URB9<=Input(27);

PhaseInc9<=Input(26 downto 22);

Gain9<=Input(21 downto 18);

URB13<=Input(27);

PhaseInc13<=Input(26 downto 22);

Gain13<=Input(21 downto 18);

URB17<=Input(27);

PhaseInc17<=Input(26 downto 22);

Gain17<=Input(21 downto 18);��

URB21<=Input(27);

PhaseInc21<=Input(26 downto 22);

Gain21<=Input(21 downto 18);

URB25<=Input(27);

PhaseInc25<=Input(26 downto 22);

Gain25<=Input(21 downto 18);

URB29<=Input(27);

PhaseInc29<=Input(26 downto 22);

Gain29<=Input(21 downto 18);

URB33<=Input(27);

PhaseInc33<=Input(26 downto 22);

Gain33<=Input(21 downto 18);��

URB37<=Input(27);

PhaseInc37<=Input(26 downto 22);

Gain37<=Input(21 downto 18);

URB41<=Input(27);

PhaseInc41<=Input(26 downto 22);

Gain41<=Input(21 downto 18);

URB45<=Input(27);

PhaseInc45<=Input(26 downto 22);

Gain45<=Input(21 downto 18);

URB49<=Input(27);

PhaseInc49<=Input(26 downto 22);

Gain49<=Input(21 downto 18);��

URB53<=Input(27);

PhaseInc53<=Input(26 downto 22);

Gain53<=Input(21 downto 18);

URB57<=Input(27);

PhaseInc57<=Input(26 downto 22);

Gain57<=Input(21 downto 18);

URB61<=Input(27);

PhaseInc61<=Input(26 downto 22);

Gain61<=Input(21 downto 18);

-- Bins 2,6,10,14,18,22,26,30,34,38,42,46,50,54,58,62 data

URB2<=Input(37);

PhaseInc2<=Input(36 downto 32);

Gain2<=Input(31 downto 28);

URB6<=Input(37);

PhaseInc6<=Input(36 downto 32);

Gain6<=Input(31 downto 28);

URB10<=Input(37);

PhaseInc10<=Input(36 downto 32);

Gain10<=Input(31 downto 28);

URB14<=Input(37);

PhaseInc14<=Input(36 downto 32);

Gain14<=Input(31 downto 28);

URB18<=Input(37);

PhaseInc18<=Input(36 downto 32);

Gain18<=Input(31 downto 28);��

URB22<=Input(37);

PhaseInc22<=Input(36 downto 32);

Gain22<=Input(31 downto 28);

URB26<=Input(37);

PhaseInc26<=Input(36 downto 32);

Gain26<=Input(31 downto 28);

URB30<=Input(37);

PhaseInc30<=Input(36 downto 32);

Gain30<=Input(31 downto 28);

URB34<=Input(37);

PhaseInc34<=Input(36 downto 32);

Gain34<=Input(31 downto 28);��

URB38<=Input(37);

PhaseInc38<=Input(36 downto 32);

Gain38<=Input(31 downto 28);

URB42<=Input(37);

PhaseInc42<=Input(36 downto 32);

Gain42<=Input(31 downto 28);

URB46<=Input(37);

PhaseInc46<=Input(36 downto 32);

Gain46<=Input(31 downto 28);

URB50<=Input(37);

PhaseInc50<=Input(36 downto 32);

Gain50<=Input(31 downto 28);��

URB54<=Input(37);

PhaseInc54<=Input(36 downto 32);

Gain54<=Input(31 downto 28);

URB58<=Input(37);

PhaseInc58<=Input(36 downto 32);

Gain58<=Input(31 downto 28);

URB62<=Input(37);

PhaseInc62<=Input(36 downto 32);

Gain62<=Input(31 downto 28);

-- Bins 3,7,11,15,19,23,27,31,35,39,43,47,51,55,59,63 data

URB3<=Input(47);

PhaseInc3<=Input(46 downto 42);

Gain3<=Input(41 downto 38);

URB7<=Input(47);

PhaseInc7<=Input(46 downto 42);

Gain7<=Input(41 downto 38);

URB11<=Input(47);

PhaseInc11<=Input(46 downto 42);

Gain11<=Input(41 downto 38);

URB15<=Input(47);

PhaseInc15<=Input(46 downto 42);

Gain15<=Input(41 downto 38);

URB19<=Input(47);

PhaseInc19<=Input(46 downto 42);

Gain19<=Input(41 downto 38);��

URB23<=Input(47);

PhaseInc23<=Input(46 downto 42);

Gain23<=Input(41 downto 38);

URB27<=Input(47);

PhaseInc27<=Input(46 downto 42);

Gain27<=Input(41 downto 38);

URB31<=Input(47);

PhaseInc31<=Input(46 downto 42);

Gain31<=Input(41 downto 38);

URB35<=Input(47);

PhaseInc35<=Input(46 downto 42);

Gain35<=Input(41 downto 38);��

URB39<=Input(47);

PhaseInc39<=Input(46 downto 42);

Gain39<=Input(41 downto 38);

URB43<=Input(47);

PhaseInc43<=Input(46 downto 42);

Gain43<=Input(41 downto 38);

URB47<=Input(47);

PhaseInc47<=Input(46 downto 42);

Gain47<=Input(41 downto 38);

URB51<=Input(47);

PhaseInc51<=Input(46 downto 42);

Gain51<=Input(41 downto 38);��

URB55<=Input(47);

PhaseInc55<=Input(46 downto 42);

Gain55<=Input(41 downto 38);

URB59<=Input(47);

PhaseInc59<=Input(46 downto 42);

Gain59<=Input(41 downto 38);

URB63<=Input(47);

PhaseInc63<=Input(46 downto 42);

Gain63<=Input(41 downto 38);

DFF0: DFlipFlop port map (CLK, LD, RESET, PRB, PRB1, PRB1not);

DFF1: DFlipFlop port map (CLK, LD, RESET, PRB1, PRB2, PRB2not);

DFF2: DFlipFlop port map (CLK, LD, RESET, PRB2, PRB3, PRB3not);

DFF3: DFlipFlop port map (CLK, LD, RESET, PRB3, PRB4, PRB4not);

DFF4: DFlipFlop port map (CLK, LD, RESET, PRB4, PRB5, PRB5not);

DFF5: DFlipFlop port map (CLK, LD, RESET, PRB5, PRB6, PRB6not);

DFF6: DFlipFlop port map (CLK, LD, RESET, PRB6, PRB7, PRB7not);

DFF7: DFlipFlop port map (CLK, LD, RESET, PRB7, PRB8, PRB8not);

DFF8: DFlipFlop port map (CLK, LD, RESET, PRB8, PRB9, PRB9not);

DFF9: DFlipFlop port map (CLK, LD, RESET, PRB9, PRB10, PRB10not);

DFF10: DFlipFlop port map (CLK, LD, RESET, PRB10, PRB11, PRB11not);

DFF11: DFlipFlop port map (CLK, LD, RESET, PRB11, PRB12, PRB12not);

DFF12: DFlipFlop port map (CLK, LD, RESET, PRB12, PRB13, PRB13not);

DFF13: DFlipFlop port map (CLK, LD, RESET, PRB13, PRB14, PRB14not);

DFF14: DFlipFlop port map (CLK, LD, RESET, PRB14, PRB15, PRB15not);