NPS logo NPS title



Peter R. Ateshian
Faculty Associate - Research
Department of Electrical and Computer Engineering
Graduate School of Engineering and Applied Sciences
Monterey, CA 93943
Phone: 831-656-2255
Email: prateshi (at) nps.edu
EDUCATION:
MEng - UC Berkeley, 1979
EECS & Business Administration
BS - UC Berkeley, 1976
Engineering Science
NPS EXPERIENCE:
  • Research: C(sP3) diamond on Silicon wafer technology for InP/GaN devices LBL/NPS/SP3
      RSNS 0.18u CMOS folded A/D 8bit converter design NPS/ONR
      MMALV
      Real-time speech recognition using aural canal
      ARM System on Chip (SoC)
  • Teaching: EC2200 EC2220 EC2300 EC2500 EC2820 EC3820 EC4580 EO2402 EO2525 EO2513 EO3535
  • Course Development: EC2220 EC2840 EC3800 EC3820
OTHER EXPERIENCE:
  • Veteran of Silicon Valley California for 25 years in Electronic Design Automation (EDA/CAD), Integrated Circuit designer in VLSI/ULSI Mixed Signal systems. AMD K9 processor RET (resolution enhancement technology) with Calibre DFM (design for manufacture) suite of Physical verification tools. Intel ICG multiple network processor products taken to production after integrating EDRAM (embedded DRAM) IP cores. SoC designs with Conexant Systems, MindSpeed and Skyworks using ARM7 and ARM9 cores. Seven SPARC processor designs over eight years at Sun Microsystems including the first MCM quad processor MP systems. Behavioral and Logic Synthesis EDA/CAD designs for ASIC and FPGA/CPLD clients (Apple, Hitachi, Silicon Graphics, Cisco Systems).Static Mixed and multi mode timing analysis for Full custom digital design cleints (SUN, Fujitsu, AT&T, Texas Instruments, HMSI). DSP Cyclotomic and Switched Capacitor Filter designs for digital and sampled analog signal processing integrated circuits for telecommunications clients (Plantronics, Reticon, Ford Microelectronics/Visteon, Siemens, Phlips Research Labs/Signetics).
TEACHING INTERESTS:
  • Course development using more commercial EDA tools for Formal Verification (FV) and DFT in Advanced Mixed Signal SoC designs
  • DFT (Design for Testability)
RESEARCH INTERESTS:
  • Photonic A/D conversion for RF signal sampling and analysis, Mach Zehnder Interferometers, 0.1- 5 micron Nanotechnlogy manufacturing technology for molds and transfer masks, Chromatorphore nanotechnology C-Si substrates for GaN & InP microwave designs. Light Emitting Transistor, 500GHz Bipolar Junction transistors, ECC design redundancy for ultra reliable Networks on Chip.
AWARDS:
  • IEEE Student Chairman UC Berkeley Chapter, Eta Kappa Nu, Tau Beta Pi
  • Acheivement Awards - Mentor Graphics Corp (several)
BOARDS/MEMBERSHIPS:
  • Bio-Robots Inc
  • Xtrm Designs LLC
  • UCB Alumni Assocations
SELECTED PUBLICATIONS:
  • CICC 1983 Switched Capacitor Filter Array - the analog to digital gate arrays.
KEYWORDS/TECHNOLOGIES:
  • Keywords: MZI, Photonic, Chromatorphore, Nanotubes, LET, SoC, NoC, C-Si, sP3 diamond, EDA, VLSI, SPARC, ARM, DFT, Formal, physical verification, VLIW DSP, Multi-Processor.



The pages on this site are dynamic, and are created by a script. Contact Faculty Vitae Admin to report incomplete or incorrect data.
NPS Home | Privacy Policy | Copyright / Accessibility / Section 508 | Contact Webmaster |
This is an Official U.S. Navy Website